Esra İnce | Barış Karakaya* | Mustafa Türk
© 2022 IIETA. This article is published by IIETA and is licensed under the CC BY 4.0 license (http://creativecommons.org/licenses/by/4.0/).
OPEN ACCESS
Security and privacy problems in communication systems and social media platforms where digital image/video are shared almost always, have attracted researchers interest on information security. Starting from this point of view, a novel one-dimensional chaotic maps based pseudo random bit generator is proposed to make a significant contribution to the literature about protection of personal data in any network. Electronic circuit realizations of Logistic and Tent maps as entropy source are designed on Orcad-Pspice environment and state variables are inputted to novel post-processor algorithm. The rest of main blocks of proposed pseudo random bit generator design are built up fixed-point binary conversion algorithm, XOR processor and H function post-processor. The generated pseudo random bit series are tested by using NIST 800.22 statistical test suite and applied to color image encryption in order to show the effectiveness of proposed design. Cryptanalysis processes such as histogram, NPCR-UACI and correlation analysis are demonstrated. Analysis results show that the proposed design can be used successfully in many secure communication and media transmission applications.
chaotic map, fixed-point conversion, post-processor, random number bit generator, statistical tests
Nowadays, image, text and video encryption technology has a great importance for social media, communication systems and cyber-security systems. Especially, the secure communication between most important units of governments such as military are face to enemy attacks. Due to this intensification of sharing digital information, images and videos through any communication environment, the most important subject to be concentrated is secure communication [1-4]. Therefore, researchers show great interest in encryption techniques to be ensure on secure communication. Since all encryption techniques require private key value or bits, the security of a cryptographic system relies on the private key. Compared with traditional encryption algorithms, chaos-based hardware architectures have demonstrated outstanding performance with proven true random bit generation as private key and ability of increased security and privacy of the communication system [5-8]. In this study, it is aimed to ensure information confidentiality and secure communication especially in military areas by using chaotic hardware circuit structures based encryption methods and algorithms.
In the literature, there are so many studies on chaos based image, video and text encryption applications. Especially, chaotic map based encryption techniques have been utilized by several researchers. A modified Logistic map based encryption is proposed by Han [9] in 2019 to overcome the problems of small key space and poor security. An image cipher algorithm is proposed by Kumar et al. [10] in 2022 that uses Logistic and Arnold’s cat maps by shuffling the pixels of an input color image. There are also several studies using electronic circuit realizations of chaotic dynamical systems as entropy source such as the study [11] proposed by Volos et al. in 2013, where true random bits are generated from the synchronization results of nonlinear Chua’s like autonomous circuit and bits sequence has then been used to encrypt and decrypt gray-scale images. Chaotic time-series obtained from a non-equilibrium system are used to construct S-boxes and develop an image encryption application by Wang et al. [12] in 2019. Furthermore, researchers proposed to use different chaotic dynamical systems as entropy source; circuit realization, control design and image encryption application of their proposed system such as extended Lü system [13], autonomous RLCC-Diodes-Opamp chaotic oscillator [14, 15], modified Chua’s circuit [16], a new chaotic jerk system [17] and chaotic one dimensional maps [18-24].
There are also so many studies using Substitution boxes (S-boxes) [21, 25, 26] and post-processors to provide the diffusion and permutation of the image pixels such as XOR [27, 28], H function [29], Von Neumann corrector [30, 31] and so on. In this study, permutation and diffusion processes for encrypted image with generated random bits are provided by using fixed-point number conversion, XOR and H function post-processor all together. In the proposed technique, the state variable values of Logistic and Tent maps are converted to their fixed-point binary equivalence, then the bit streams for each state variables are inputted to XOR logical function, sampling and H function respectively in order to generate statistically random bits.
The main objective of this paper is to generate pseudo random bit from the electronic circuit realization of Logistic and Tent maps. The electronic circuits designed and simulated on Orcad-Pspice environment. In order to implement the electronic circuits of chaotic map equations, general-purpose operational amplifiers and special integrated circuits (IC) such as AD633 and LF398 are used.
Herewith this introduction, chaotic Logistic and Tent maps are defined and the trends of their state variables are given in Section 2. In Section 3, electronic circuit realizations of Logistic and Tent maps are designed and map equations are detailed with the equivalent form active and passive circuit elements. The main blocks of proposed pseudo random bit generator (PRBG) design; entropy source, fixed-point binary conversion algorithm, XOR processor, bit accumulator, sampling, H function post-processor and statistical test results are detailed in Section 4. The generated pseudo random bit (PRB) series are applied to color image encryption in order to show the effectiveness of PRBG and cryptanalysis processes such as histogram, NPCR-UACI and correlation analysis are demonstrated in Section 5. At the end, final section concludes the paper.
In this section, definitions of Logistic map and Tent map are detailed with the parameters and dynamics of systems. The Logistic and Tent maps are 1D chaotic maps and the state variable of each shows various dynamic properties with the equations below;
$x _{\log ( n +1)}= r * x _{\log ( n )} *\left(1- x _{\log ( n )}\right)$ (1)
$x_{\text {tent }( n +1)}=\left\{\begin{array}{cl} a * x _{\operatorname{tent}( n )} & x _{\operatorname{tent}( n )}<0.5 \\ a *\left(1- x _{\operatorname{tent}( n )}\right) & x _{\operatorname{tent}( n )} \geq 0.5\end{array}\right.$ (2)
where, r and a are control parameters of maps, chaotic behavior is obtained rÎ[3.5, 4] and aÎ[1.5, 2] for each map respectively. The initial condition of state variable varies between the same value, xÎ[0, 1], for both Logistic map and Tent map. The variation of state variables is given in Figure 1 for r=3.9, a=1.99 under the same initial condition for both is x(0)=0.61.
Figure 1. The trend of state variables of Logistic (xlog) and Tent (xtent) maps
As it is clearly appeared in Figure 1 that there is a noise like behavior from the output of each chaotic map. Recently, chaotic maps are studied much in image/video encryption applications because their simple equations and very sensitive structure to initial conditions.
Starting from the mathematical model of any linear or nonlinear system, it is always possible and easy to realize an equivalent electronic circuit that obeys to the same set of equations [32]. The aim of this study is to generate secure pseudo random bits using electronic circuit realizations of 1D chaotic maps. The circuitries are designed on Orcad-Pspice environment to obtain the variation of state variables iteratively. Most researchers, studying on chaotic electronic circuits, design the circuits by using active circuit elements such as operational amplifier, analog multiplier, multiplexer and standard passive circuit elements such as resistor, capacitor and so on. From the mathematical model of chaotic systems to the electronic circuit, the most important active circuit element is operational amplifier. Especially for the discrete chaotic systems i.e. chaotic maps, sample and hold integrated circuit (special operational amplifiers) is very essential. The electronic circuit realizations of Logistic and Tent maps are designed and simulated on Orcad-Pspice environment as given in Figures 2 and 3 according to the observations made during the numerical analysis on MATLAB.
In the design stage of electronic circuits, general purpose operational amplifiers are used. On the other hand, LF398 integrated circuit is used for sample and hold operations because the chaotic maps have discrete dynamical equations. In order to implement the mathematical model of chaotic maps, classical definitions of op-amps and the mathematical equations of special integrated circuits such as AD633 and LF398 have to be analyzed.
Figure 2. The electronic circuit realization of logistic map on Orcad-Pspice environment
The LF398 is a monolithic sample and hold circuit that is a unity-voltage gain follower that is used in both Logistic and Tent experimental circuits. A hold capacitor is connected output pin of LF398 to obtain sampled voltage on it. TTL compatible square wave (clk) signal provided from the signal generator is used to trigger the first LF398 (on the right). The second LF398 (on the left) is triggered by the logic inverse of this square wave (Y). A common emitter NPN bipolar 2N2222 transistor is used to provide inverse of square wave. The initial value for circuit operation is applied to the hold capacitor connected to the first LF398 in both electronic circuits. The new value of state variable (Xn1) is generated in once every period of the TTL signal. The AD633 is a functionally complete analog multiplier, includes high impedance, differential X and Y inputs, and a high impedance summing input (Z). The transfer function of the AD633 IC used in the electronic circuit of the Logistic map is as follow:
$W =\frac{( X 1- X 2) *( Y 1- Y 2)}{10 V }+Z$ (3)
where, W is the output of multiplier.
Figure 3. The electronic circuit realization of Tent map on Orcad-Pspice environment
The list of experimental circuit elements is given in Table 1 while the values of all passive circuit elements and voltage supplies are detailed in Table 2.
Table 1. The list of experimental circuit elements used in electronic circuits
|
Tent Map |
Logistic Map |
||
|
U1, U2, U3, U4, U5 |
TL082 |
U1, U2, U4 |
TL082 |
|
U6, U7 |
LF398 |
U3 |
AD633 |
|
Q1 |
2N2222 |
U5, U6 |
LF398 |
|
D1, D2 |
1N4148 |
Q1 |
2N2222 |
Table 2. The values of circuit elements used in electronic circuits
|
Tent map |
Logistic map |
||
|
R1 |
100 kΩ |
R1, R3, R5, R6, R11 |
10 kΩ |
|
R2, R3, R4, R5, R6, R8, R10, R11, R12, R16 |
1 kΩ |
R2 |
50 kΩ |
|
R7 |
4 kΩ |
R4 |
15.6 kΩ |
|
R9 |
2.1 kΩ |
R7, R8, R9, |
2.2 kΩ |
|
R13, R14, R15 |
2.2 kΩ |
R10 |
1 kΩ |
|
R17 |
10 kΩ |
C1, C2 |
0.01 µF |
|
C1, C2 |
0.01 µF |
Vref |
5 V |
|
Vref |
-0.5 V |
VCC |
+15 V |
|
VCC |
+15 V |
VEE |
-15 V |
|
VEE |
-15 V |
|
|
The conversion of mathematical models of chaotic maps to electronic circuits regarding basic circuit rules and by using Eq. (1), (2) and (3), Figure 2 and Figure 3 can be analyzed. The output (Xn1) of Logistic map related to the input (Xn) is analyzed node by node through the following equations:
$A=-\frac{R_2}{R_1} X_n$ (4)
$B =-\frac{R_4}{R_3} A$ (5)
$C=-\frac{R_6}{R_5} A$ (6)
$X _{n 1}=\frac{ B \left(v_{r e f}-C\right)}{10}$ (7)
$X _{n 1}=\frac{\frac{R_4 R_2}{R_3 R_1} X_n\left(V_{r e f}-\frac{R_6 R_2}{R_5 R_1} X_n\right)}{10}$ (8)
$X _{n 1}=\frac{1}{10} \frac{R_4}{R_3} \frac{R_2}{R_1} X_n V_{\text {ref }}-\frac{1}{10} \frac{R_4}{R_3} \frac{R_2^2}{R_1^2} \frac{R_6}{R_5} X_n^2$ (9)
$X _{n 1}=3.9 X _n\left(1- X _n\right)$ (10)
where, Xn1 stands for next iterative value of Logistic map while Xn is actual. The output (Xn1) of Tent map related to the input (Xn) is analyzed node by node through the following equations:
$A =\left(\frac{R_2}{R_1}+1\right) X_n$ (11)
$B =-\frac{R_5}{R_4} A-\frac{R_5}{R_3} V_{r e f}$ (12)
$C =-\frac{R_7}{R_6} B$ (13)
$D =-\frac{R_9}{R_{ g }} A$ (14)
$X _{n 1}=-\frac{R_{12}}{R_{10}} D-\frac{R_{12}}{R_{11}} C$ (15)
$X _{n 1}=\frac{R_{12}}{R_{10}} \frac{R_9}{R_8}\left(\left(\frac{R_2}{R_1}+1\right) X_n\right)+\frac{R_{12}}{R_{11}} \frac{R_7}{R_6}\left(-\frac{R_5}{R_4}\left(\left(\frac{R_2}{R_1}+\right.\right.\right.$1) $\left.\left.X_n\right)-\frac{R_5}{R_3} V_{\text {ref }}\right)$ (16)
$X_{n 1}=\frac{R_{12}}{R_{10}} \frac{R_9}{R_8} \frac{R_2}{R_1} X_n+\frac{R_{12}}{R_{10}} \frac{R_9}{R_8} X_n+\frac{R_{12}}{R_{11}} \frac{R_7}{R_6}\left(-\frac{R_5}{R_4} \frac{R_2}{R_1} X_n-\right.$$\left.\frac{R_5}{R_4} X_n-\frac{R_5}{R_3} V_{\text {ref }}\right)$ (17)
$X_{n 1}=\frac{R_{12}}{R_{10}} \frac{R_9}{R_8} \frac{R_2}{R_1} X_n+\frac{R_{12}}{R_{10}} \frac{R_9}{R_8} X_n-\frac{R_{12}}{R_{11}} \frac{R_7}{R_6} \frac{R_5}{R_4} \frac{R_2}{R_1} X_n-$$\frac{R_{12}}{R_{11}} \frac{R_7}{R_6} \frac{R_5}{R_4} X_n+\frac{R_{12}}{R_{11}} \frac{R_7}{R_6} \frac{R_5}{R_3} V_{\text {ref }}$ (18)
$X _{n 1}=\frac{R_{12}}{R_{10}} \frac{R_9}{R_8} X_n-\left\{\begin{array}{cc}0, & X_n<\frac{R_4}{2 R_3} \\ \frac{R_{12}}{R_{11}} \frac{R_7}{R_6}\left(\frac{R_5}{R_4} X_n-\frac{R_5}{2 R_3}\right), & X_n \geq \frac{R_4}{2 R_3}\end{array}\right.$ (19)
where, Xn1 stands for next iterative value of Tent map while Xn is actual. As the all resistor values are taken into account in Eq. (19), the value of the bifurcation parameter a can be fixed at certain values by simply adjusting the R7 and R9 resistor connected to feedback resistor in the operational amplifiers of U3 and U4. The relationship between the resistors R7 and R9 with the value of a≅2 and the simplest equation for Tent map can be obtained in Eq. (20) below.
$X_{n 1}=\left\{\begin{array}{cc}a X_n & X_n<\frac{1}{2} \\ a\left(1-X_n\right) & X_n \geq \frac{1}{2}\end{array}\right.$ (20)
As it is clearly seen in the equations above, the electronic circuit realization of any mathematical models can be installed by using basic rules of common electronic components and special integrated circuits. The trend of the state variables of discrete chaotic maps are illustrated in Figure 4 for the same initial condition value of 0.61 V.
Figure 4. The trend of the state variable of a) Logistic map and b) Tent map for the same initial condition value of 0.61 V
The trends of output for each chaotic maps are discrete and noise-like behavior can be observed. The new value of state variables is produced iteratively at every 20 μs which is the period of trigger digital signal (clk).
The aim of this study is to generate secure pseudo random bits using electronic circuit realizations of 1D discrete chaotic maps. The proposed PRBG design consists of discrete Logistic and Tent maps as entropy source, fixed-point binary conversion algorithm, XOR processor, bit accumulator, sampling and H function post-processor as illustrated in Figure 5. The values of state variables are imported to MATLAB platform in order to apply fixed-point binary conversion algorithm and the rest of the proposed design processes.
The design has chaotic discrete maps as entropy source that are simulated on Orcad-Pspice environment in order to obtain almost 1 million data. The simulation results are 995654 fractional numbers in double format for each chaotic map. In order to provide diffusion requirement of random bit generator securely, the value of state variables is converted to binary form by using Q1.15 unsigned fixed-point fractional number representation format where most significant bit is discarded because of state variables of Logistic and Tent maps are in the range of [0,1]. The whole diffusion processes (conversion, XOR, sampling, H function post-processor) are illustrated in Figure 5 and detailed by giving the pseudo code for each process in Table 3.
The pseudo random bit stream is in 7467345-bit length that is generated by using the chaotic maps as entropy source. In order to show effectiveness of the proposed PRBG design, the bit stream is subjected to statistical randomness tests. In to analyze statistically randomness of any number or bit stream can be tested by using NIST 800.22 test suite that is explained in details in the study of Rukhin et al. [33]. In this study, statistical randomness tests of generated bits are carried out by the NIST 800.22 test suite and Table 4 demonstrates these statistical tests results.
Figure 5. Block diagram of the proposed PRBG design
Table 3. The pseudo-code of fixed-point conversion, XOR & sampling and H function post-processor.
|
Algorithm 1: Q1.15 unsigned fixed-point fractional number conversion of chaotic map outcomes (fixed-point binary conversion) Input: State variables of chaotic Logistic (xlog) and Tent (xtent) maps generated on Orcad-Pspice environment Output: Unsigned fixed-point fractional numbers in 15-bit length for each decimal number input q=quantizer (‘ufixed’, [16 15]) for i = 1: 1: 995654 xlog_f = num2hex (q, xlog (:)); xtent_f = num2hex (q, xtent (:)); xlog_frc = hex2bin (q, xlog_f); xtent_frc = hex2bin (q, xtent_f); x_l_f (i) = xlog_frc (2:16); x_t_f (i) = xtent_frc (2:16); end Algorithm 2: Process for XOR function and sampling by 2 (XOR logic operation and sampling) Input: 995654 data each one of is in 15-bit length Output: XORed and sampled data in 7467345-bit length for i=1: 2: 995654 xlogtent ((i-1) * 15+1: i*15, 1) =XOR (x_l_f (i), x_t_f (i)); end Algorithm 3: H function as a post-processor Input: Data in 7467345-bit length Output: Pseudo random bit (PRB) stream in 7467345-bit length for i = 1: 1: 7467345 x_hash = xlogtent ((i-1) * 16 + 1: i*16); a1 = x_hash (1:8); a2 = x_hash (9:16); PRB ((i-1) * 8+1: i * 8) = XOR (XOR (a1, rotateleft (a1,1)), a2); end |
Table 4. Statistical test results of the proposed PRBG design outputs
|
NIST Tests (3733672 bit) |
PRB1 (first 1572864 bit) |
Result |
PRB2 (last 1572864 bit) |
Result |
|
Frequency (monobit) Test |
0.5541 |
Passed |
0.4819 |
Passed |
|
Frequency Test within a Block |
0.3318 |
Passed |
0.62 |
Passed |
|
Runs Test |
0.5528 |
Passed |
0.2244 |
Passed |
|
Test for the Longest Run of Ones in a Block |
0.605 |
Passed |
0.711 |
Passed |
|
Binary Matrix Rank |
0.0565 |
Passed |
0.5931 |
Passed |
|
Discrete Fourier Transform Test |
0.6369 |
Passed |
0.7427 |
Passed |
|
Non-overlapping Template Matching Test |
0.1652 |
Passed |
0.0634 |
Passed |
|
Overlapping Template Matching Test |
0.2109 |
Passed |
0.7234 |
Passed |
|
Maurer’s Universal Statistical Test |
0.5814 |
Passed |
0.5411 |
Passed |
|
Linear Complexity Test |
0.1394 |
Passed |
0.091 |
Passed |
|
Serial Test 1/2 |
0.0231 / 0.277 |
Passed |
0.525 / 0.4394 |
Passed |
|
Lempel Ziv Test |
77623 / 2 / 1 |
Passed |
77620 / 2 / 1 |
Passed |
|
Approximate Entropy Test |
0.013 |
Passed |
0.5903 |
Passed |
|
Cumulative Sums Test |
0.8263 |
Passed |
0.2575 |
Passed |
|
Random Excursions Test |
0.0941 |
Passed |
0.3048 |
Passed |
|
Random Excursions Variants Test |
0.0466 |
Passed |
0.3286 |
Passed |
According to Table 4, it can be clearly seen that generated pseudo random bit series passed all tests successfully. After proving the statistically randomness of bit stream, an image encryption application is carried out with the analysis and results to show the effectiveness of the proposed PRBG design.
The image encryption stage of this study consists of two application phases. In first, the bit stream obtained proposed pseudo bit generator design is split into two parts each has 1572864 bit (PRB1 and PRB2) and statistically random as proved in Table 4. Then, each random bit stream is inputted to XOR function with one original test image. Since the size of original test image is 256x256 in RGB format, required random key bit length is determined as 256 rows x 256 columns x 3 channels x 8 bit = 1572864 bit. The original test image, encrypted image with PRB1 and encrypted image with PRB2 which are in the same size are illustrated in Figure 6.
Figure 6. a) The original test image b) Encrypted image with PRB1 c) Encrypted image with PRB2
Figure 7. Histogram analysis for a) original image b) encrypted image with PRB1 c) encrypted image with PRB2
Most of researchers studying on image encryption use cryptanalysis processes in order to show the effectiveness of their proposed random bit designs such as histogram, NPCR-UACI and correlation analysis. Histogram analysis is the graphical measure of the distribution of pixel values on an image. Especially for the image encryption applications, the algorithm of histogram analysis should follow two criteria. First, histograms of original and encrypted images must differ from significantly one to another. Second, the distribution of pixel values in encrypted image should be uniform [34, 35]. The histograms of original test image, encrypted image with PRB1 and encrypted image with PRB2 are given in Figure 7.
When the histogram plots are examined, it is seen that the original test image and encrypted image with both PRB1 and PRB2 are completely different from each other. Also, the distribution of pixel values in encrypted images are uniform.
In addition to the histogram analysis, there are also two statistical tests which provide effectiveness of encryption algorithm on image encryption applications. These measurements are Number of Pixels Change Rate (NPCR) and Unified Average Changing Intensity (UACI) tests where a value of 0.99 for the NPCR test and a value of 0.33 for UACI test are considered as success criteria. The calculated NPCR and UACI values for the encrypted image shown in Figure 6 are 0.995961507161458 and 0.334804133495292, respectively. It is clearly observed that the calculated test results are very close to the success criteria.
Figure 8. Correlation distribution of a) the original test image b) encrypted image with PRB1 and c) encrypted image with PRB2; along diagonal, horizontal and vertical direction where each one of them is indicated as a column, respectively
Correlation analysis shows the correlation of adjacent pixels in an image along diagonal (D), horizontal (H), vertical (V) directions. This analysis tool is also used to verify the inferences the correlation distributions of the original and encrypted images. The correlation distribution of the original test image is generally high. Therefore, the encryption algorithm or design must remove the correlation between adjacent pixels as much as possible [36]. Figure 8 shows the correlation distribution of original test image in Figure 6 (a) and the encrypted images with the PRB1 and PRB2 given in Figure 6 (b) and Figure 6 (c), respectively.
All the results of the statistical tests and analyses reveal that the pseudo random bit generated from chaotic discrete maps can be used in image/media encryption applications securely. Furthermore, the proposed image encryption application passes all the both statistical and differential attack tests.
The proposed design has two 1D chaotic maps and their electronic circuit on Orcad-Pspice environment to observe the effectiveness of chaos based image encryption systems. The design has passed all the statistical tests successfully and the metrics of cryptanalysis have been verified. The proposed post-processor blocks are built up fixed-point binary conversion algorithm, XOR processor and H function post-processor. Considering the results obtained and given in the previous sections, it can be concluded that the proposed design can be used successfully in communication and media transmission systems as it has complex algorithms, trustable diffusion and permutation processes.
As a future study, it is aimed to design a secure hardware-based image/video encryption system for military unmanned aerial vehicles by using a combination of chaotic dynamic system and user biometric data.
This work is supported by The Scientific and Technological Research Council of Turkey (TUBITAK) Project Number: 121E003 and also produced from the part of Esra İnce’s Doctoral Thesis.
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