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This paper proposed a new topology of a symmetric singlephase multilevel inverter with the smaller number of semiconductor switches and optimized lowfrequency control methods to optimize the Total Harmonic Distortion. A ninelevel single phase output is obtained by eight number of active semiconductor switches, four diodes and four capacitors from two asymmetrical dc sources. The selected harmonic order in the output voltage is eliminated by the PWM (SHEPWM) based on selective harmonic elimination. To optimize the switching angles, an ant colony optimization is introduced. The proposed SHEPWM and ant optimization are implemented and tested for THD on the SIMULINK platform. The proposed approach offers less THD and is best suited to highpower applications with medium voltage.
THD, SHEPWM, ACO, multilevel inverter, optimization, symmetric Inverter
Inverter is a system that converts the acceptable voltage and output frequency from DC to AC. There are some problems in inverters including lower efficiency, high dv/dt, higher power losses and large THD [1]. A multilevel inverter is designed to solve these issues. With a threelevel converter, the word Multilevel has begun, the cascaded multilevel inverter is currently in use [2]. The output of the multilevel inverter has lower harmonics than the normal output voltage of the bipolar inverter. Multilevel inverters are mainly known as a clamped diode, Flying condenser, and cascaded MLI [2, 3]. The control scheme of cascaded MLI is simple compared to other MLIs since a clamping diode and a flying condenser are not needed [4]. For more than three decades, multilevel inverters are under research and development, and successful industrial applications have been discovered [5]. Nonetheless, this is still an emerging technology, and many fresh developments have been reported in recent years [68]. Multilevel inverters have drawn growing interest, with the key reasons being increasing power levels, improved harmonic performance and reduced emissions of electromagnetic interference (EMI) that can be preserved with several dc stages synthesizing the output voltage waveform [7]. In systems like industrial variablevoltage drives, EVs and photovoltaic networks connected to the grid. The ongoing work offers an alternative to the design of an effective multilevel topology for high and mediumpower applications.
Advanced Multilevel inverters now use fewer components and smaller carrier signals as compared with traditional multilevel inverters. A composite topology is presented in this paper having separate level generating part and polarity generating parts [8]. To increase the output of multilevel inverters in hybrid topology, first positive rates are produced with highfrequency switches and then the voltage portion is reversed with lowfrequency switches [912]. As a result, the control circuit complexity for higher levels is significantly reduced. Selective harmonic pulse width modulation (SHEPWM) technique with Ant Colony optimization has been used to simulate a single phase 9level hybrid inverter. The inverter performance is evaluated about harmonic distortion (THD) [1315]. The purpose of this research is to minimize the THD of output voltage by using low switching frequency PWM (SHEPWM) and optimization algorithm in reduced switch symmetrical 9level inverter. The harmonic distortion generated by the proposed inverter is significantly lower, around 5% by the results obtained from simulation. This paper is organized as follows. Firstly, introduction to the multilevel inverter literature, Section2 describes the proposed 9level symmetric inverter topology, Section3 presents selective harmonic eliminationbased control of proposed inverter, Section4 presents results & discussions, and finally section5 concludes the research results.
The proposed inverter's schematic design is shown in Figure 1, which consists of two modules, namely a module for level generation and a module for voltage reversal/polarity generation. Polarity generation module is an Hbridge that reverses the polarity of output for each half cycle of operation, whereas the level generating module will generate higher levels from the dc sources that can extend up to ' n ' levels. Symmetric dc sources are used for the inverter input, where each source is divided into two equal parts by using similar condensers to increase the higher output level from less dc sources. A MOSFET is used for the circuit design and the diodes used in the circuit to prevent the short circuit of the sources [16, 17].
Relation between the components used in the circuit design given as follows.
No. of capacitors (Nc) = 2 Nv,
Where, Nv = No. of voltage sources
No. of Switches (Ns) = Nc + 4
No. of diodes (Nd) = Nc
No. of levels (Nstep) = 2Nc + 1
There are nine modes of operation of this inverter to achieve the required 9level output Vo; the first four modes of operation give the positive levels of voltages, V/2, V, 3V/2, 2V and next four modes of operation give the negative levels of voltages, V/2, V, 3V/2, 2V and ninth mode ‘0V’is obtained by switching sequence mentioned in Table 1. All these modes of operation are presented in Figure 2, where current flow paths are highlighted in each mode of operation.
These eight operating modes along with the ‘0’V Operating mode is listed in table with respective output voltage levels.
Figure 1. Proposed symmetric 9level inverter
Table 1. Switching sequence of the all modes of operations
Mode 
S1 
S2 
S3 
S4 
S5 
S6 
S7 
S8 
O/P Voltage 
I 
1 
0 
0 
0 
1 
1 
0 
0 
V/2 
II 
0 
1 
0 
0 
1 
1 
0 
0 
V 
III 
0 
0 
1 
0 
1 
1 
0 
0 
(3/2)V 
IV 
0 
0 
0 
1 
1 
1 
0 
0 
2V 
V 
1 
0 
0 
0 
0 
0 
1 
1 
V/2 
VI 
0 
1 
0 
0 
0 
0 
1 
1 
V 
VII 
0 
0 
1 
0 
0 
0 
1 
1 
(3/2)V 
VIII 
0 
0 
0 
1 
0 
0 
1 
1 
2V 
IX 
0 
0 
0 
0 
0 
0 
0 
0 
0 
(a): ModeI
(b): ModeII
(c): ModeIII
(d): ModeIV
(e): ModeV
(f): ModeVI
(g): ModeVII
(h): ModeVIII
Figure 2. Operating modes of proposed symmetric inverter
Harmonic reduction in the multi level inverters can be done by different modulation techniques, such as; Modulation with high frequency and modulation with low frequency. Modulation strategies with high switching frequency include; sine pulse modulation, stair cased modulation, digital pulse width modulation, phase shifted modulation etc., could remove harmonics of higher order in the inverter output [5]. But highfrequency modulation strategies will not remove harmonics of the lower order such as 3rd and 5th harmonics that are dominant in nature [9].
This condition can be solved by introducing lowfrequency configurations such as modulation of the space vector pulse width and selective harmonic pulse width modulations [10]. This paper proposed a SHEPWM to reduce the dominant harmonics of lower order and the switching losses in the proposed hybrid multilevel inverter [11]. A synthesized near sinusoidal output expected to obtain from the 9level output is shown in Figure 3.
3.1 Selective Harmonic EliminationPWM
For the above 9level wave form the four switching angles $\theta_{1}, \theta_{2}, \theta_{3}, \theta_{4}$ need to be generated. By considering the charact eristics of the waveform, these switching angles are the function of Fourier series expression reported in ref. [1821].
Figure 3. Proposed 9Level synthesized near sinusoidal waveform
The generalized multi level inverter output is expressed by Fourier expansion:
$V_0=\sum\limits_{k=1}^{\infty }{\frac{4{{V}_{dc}}}{k\pi }}\left( \cos k{{\theta }_{1}}+\cos k{{\theta }_{2}}+......+\cos k{{\theta }_{n}} \right)*\sin k\omega t$ (1)
The necessary constraint the to be satisfied the switching angles from $\theta_{1}$ to $\theta_{n}$ is:
$0 \leq \theta_{1}<\theta_{2}<\theta_{3}<\theta_{4} \ldots \ldots \ldots<\theta_{n} \leq \frac{\pi}{2}$ (2)
The number of harmonics to be removed in the inverter output is 2Ns1. The order of harmonics up to 6Ns2 for K is odd, and up to 6Ns1, for K is even, removed from the output waveform, where K is the order of harmonics. Thus with an inverter of nine levels with two DC outputs, the 5th, 7th, and 11th harmonics must be removed, and the transcendental equations to be satisfied are as follows.
$V_{1}=\cos \theta_{1}+\cos \theta_{2}+\cos \theta_{3}+\cos \theta_{4}=M I$
$V_{5}=\cos 5 \theta_{1}+\cos 5 \theta_{2}+\cos 5 \theta_{3}+\cos 5 \theta_{4}=0$
$V_{7}=\cos 7 \theta_{1}+\cos 7 \theta_{2}+\cos 7 \theta_{3}+\cos 7 \theta_{4}=0$
$V_{11}=\cos 11 \theta_{1}+\cos 11 \theta_{2}+\cos 11 \theta_{3}+\cos 11 \theta_{4}=0$ (3)
For optimum switching angles, modulation index (MI) is;
$M I=\frac{V_{1}}{\frac{16 V_{d c}}{\pi}}$ for $0 \leq M I \leq 1$ (4)
The optimization strategy for the proposed ninelevel MLI is taken into account in order to solve nonlinear transcendental equations [18, 19]. The significant step of any optimization technique is to create a fitness function, which relates to the variables to be evaluated. The main objectives are,
The magnitude of the harmonics depends on the angles of switching. To accomplish the above objectives the fitness function (FF) takes the form as follows:
$F F=100 * \frac{\left(V_{1 d}V_{1}\right)^{4}}{V_{1 d}^{4}}+\left(\frac{50}{V_{1}}\right)^{2} *\left(\frac{V_{5}^{2}}{5}+\frac{V_{7}^{2}}{7}+\frac{V_{11}^{2}}{11}\right)$ (5)
3.2 ANT Optimization for SHEPWM
Ant optimization (ACO) is the first to investigate an optimal path in an evolutionarybased on ant's behavior to find a path between their colony and food source [22, 23]. Figure 4 shows the step by step procedure to be followed to implement the Ant colony optimization algorithm. This algorithm is implemented in MATLAB for the solution of transcendental equations, which provides optimized switching angles for the proposed inverter.
Figure 4. A flow chart for Ant colony optimization
A symmetric 9level inverter is implemented using MATLAB SIMULINK software. To generate 4steps in each half cycle of output, 4sources are required. These 4sources are derived from 2dc sources using split capacitors. This topology uses a smaller number of power switches compared to other 9level topologies. The number of power switches and dc sources required to build this 9level inverter is compared with other topologies and presented in Figure 5 and in Figure 6. Figure 5 shows the variance in the number of switches needed to model the proposed inverter for different output voltage rates.
Figure 5. Comparison for number of active switches
The variation in the number of dc sources needed to model the proposed inverter for different output voltage levels is shown in the Figure 6.
Figure 6. Comparison for number of DC sources
The transcendental equations shown in Eq. (3) is solved for satisfying the fitness in Eq. (5), the switching angles of the proposed inverter is evaluated and tabulated in Table 2.
Table 2. Switching angles obtained from the Ant colony optimization algorithm
Algorithm 
MI 
Optimized Switching Angles (degrees) 
THD % 

θ_{1} 
θ_{2} 
θ_{3} 
θ_{4} 


ANT 
9.46 
19.65 
36.92 
59.45 
5.60 
The switching angles were applied to the proposed symmetric inverter and simulated for output voltage and current. Figure 7 shows the 9level output voltage of the proposed inverter and Figure 8 shows the load current waveform for RL load.
Figure 7. 9Level load waveform of proposed inverter
Figure 8. Load current waveform of proposed inverter
The THD of the output voltage is computed by analysing the load voltage waveform with Fourier analysis for maximum harmonic frequency. The magnitude of THD obtained for the output voltage is 5.6% and is satisfactory as per IEEE519 standards. The graph of THD anaylis is shown in Figure 9.
Figure 9. THD analysis of proposed inverter
This paper presented a novel symmetric inverter with reduced switches for a ninelevel inverter using MATLAB® SIMULINK. To optimize the switching angles of the multilevel inverter, a low frequency switching modulation called SHEPWM is used to reduce switching losses and THD. An optimization technique, Ant Colony optimization, is implemented and obtained the optimized angles for the semiconductor switches of the proposed circuit. In addition, less THD is achieved by adopting the Ant Colony Optimization technique. The output voltage obtained is approximately a sinusoidal wave. The inverter output voltage THD calculation indicates the THD is 5.60%. Therefore, the suggested inverter is compliant with different singlephase applications.
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