A Dual Frequency Compensation Technique to Improve Stability and Transient Response for a Three Stage Low-Drop-Out Linear Regulator

Many system-on-a-chip (SoC) applications integrate circuit blocks, such as digital, analog and radio-frequency blocks [1-4]. Charge pump regulators are commonly used to generate high voltages for lighting or memory units [5, 6]; switching converters are employed to regulate digital blocks, due to their high power efficiency [7, 8]; and low-drop-out linear voltage regulators are used to provide low noise supply voltage with very low ripple for noise sensitive blocks, such as analog/RF circuits [9, 10].  An example that highlights the present-day importance of voltage regulators and power management blocks can be found in ref. [11], where the power supply requirements for a Code-Division Multiple Access (CDMA) modem of a mobile phone are described. As shown in Figure 1, LDO regulators play a very important role in the integrated power management unit in modern portable electronic devices [11], they scales down the supply voltage to provide for many various other blocks.

An important issue in LDO voltage regulator design is stability, which has a direct impact on the transient response of this system. In addition, the downscaling of the supply voltage and the decrease of the intrinsic gain of the MOS transistor for nanometric CMOS technologies [12, 13] requires the use of multiple stages in the implementation of the LDO regulator, this degrades the close-loop response by the presence of multiple poles, hence the need to develop a robust compensation method. Compensation can be external or internal. Generally, external compensation is achieved with a high value capacitor in the order of µF [14]. As for internal compensation, Miller compensation is one of the most widely used techniques [10], but other techniques and approaches can be found in literature [15-28].

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Figure 1. Power management unit in modern portable devices [11]

In this work a novel frequency compensation technique is proposed to achieve the stability for wide range of the load current for the LDO regulator and also enhance his transient response. In section 2, a literature review of stability enhancement is summarized. In section 3, the proposed LDO regulator circuit is given and detailed analysis is performed. In section 4, the simulation results are given to show the performance of the proposed LDO regulator in terms of stability, transient response and others parameters accompanied by a comparison with previous related works. Finally, in section 5, the simulation results are given to show the performance of the proposed LDO regulator in terms of stability, transient response and others parameters accompanied by a comparison with previous related works.

3.1 Main blocks of proposed LDO regulator

The diagram block of proposed LDO regulator is shown in Figure 2, while Figure 3 gives transistor implementation of proposed error amplifier (EA). For error amplifier design, a single-ended two-stage error amplifier with fully differential input is chosen [29], it consists of M₁-M₆ transistors, bias current I_B,EA and common feedback resistor R_CM. A fully-differential PMOS M₁ input stage is used to achieve high power supply noise rejection. The third stage is composed by the PMOS pass transistor M_P to achieve low dropout voltage [10]. The feedback network is composed by the resistors R_FB1 and R_FB2. R_L is the load resistor which models the low voltage system-on-chip powered by the LDO regulator output. The load capacitor C_L is integrated on chip, which is essential to improve the transient response. V_I is the power supply input voltage, V_REF is the reference voltage provided by another sub-circuit, V_G,P represent the voltage at the gate of pass transistor M_P. V_O is the output voltage of LDO regulator. The compensation network will be clarified later in this section.

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Figure 2. Block diagram of the proposed LDO regulator

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Figure 3. Proposed error amplifier (EA)

3.2 Stability analysis 

3.2.1 Uncompensated frequency response

To determine the uncompensated open-loop transfer function, of the proposed LDO regulator system, defined by Eq. (1), a small signal model is established and it is represented in Figure 4. By applying the Kirchhoff current laws, we obtain the transfer function H_ol,u(s) given by Eq. (2). Where, H_0,u is the DC gain given by Eq. (3), where β is the feedback factor expressed by Eq. (4). g_m1 is the transconductance of the EA first stage which is equal to that of transistor M₁ and R_O1,EA represents the output resistance of the EA first stage expressed by Eq. (5), where r_o1 and r_o2 represent the small output resistances of transistors M₁ and M₂, respectively. g_m3 and g_m,P represent the transconductance of EA second stage, which is equal to that of transistor M₃, and the transconductance of pass transistor M_P, respectively. r_o6 is the small signal output resistance of EA second stage which is equal to small signal output resistance of transistor M₆. R_O is the output resistance of LDO regulator given by Eq. (6), where r_o,P is the output resistance of M_P. Note that s denotes the complex variable of Laplace.

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Figure 4. Small signal model of the proposed uncompensated LDO

${{H}_{ol,u}}(s)=\frac{{{v}_{fb}}}{{{v}_{ref}}}$         (1)

${{H}_{ol,u}}(s)=\frac{{{H}_{0,u}}(1+\frac{s}{{{z}_{RHP}}})}{(1-\frac{s}{{{p}_{d}}})(1-\frac{s}{{{p}_{nd}}})(1-\frac{s}{{{p}_{3}}})}$             (2)

${{H}_{0,u}}=-\beta {{g}_{m1}}{{g}_{m3}}{{g}_{m,P}}{{R}_{O1,EA}}\quad{{r}_{o6}}{{R}_{O}}$            (3)

$\beta =\frac{{{R}_{FB2}}}{{{R}_{FB1}}+{{R}_{FB2}}}$            (4)

${{R}_{O1,EA}}={{r}_{o1}}//{{r}_{o2}}//{{R}_{CMFB}}$                (5)

${{R}_{O}}={{r}_{o,P}}//({{R}_{FB1}}+{{R}_{FB2}})//{{R}_{L}}$             (6)

The transfer function contains a right half-plane (RHP) zero z_RHP given by Eq. (7), where C_gd,P is the parasitic drain-to-source capacitance. The frequency location of z_RHP changes with load current I_L (or value of R_L), because g_m,P and C_gd,P change with I_L and this is due to the fact that M_p changes the region of operation according to the variation range of I_L [9].

${{z}_{RHP}}=\frac{{{g}_{m,P}}}{{{C}_{gd,P}}}$         (7)

According to Eq. (2), the transfer function contains three left half-plane (LHP) poles p_d, p_nd and p₃, where their locations change relatively with the load current. The dominant pole p_d is located at the gate node of M_P (v_g,P voltage in Figure 4) due to the large value of C_G,P and r_o6, where C_G,P represents the total capacitance connected between the M_P gate and the small signal ground. The non-dominant pole p_nd is located at the output node (v_o voltage in Figure 4). The third pole p₃ represents the high frequency pole and it’s located at the first stage output node of EA (v₁ voltage in Figure 4). This last pole is independent of the load current and therefore does not affect the stability. For the proposed LDO regulator design, M_p operates in sub-threshold region when the load current is at its minimum value I_L,min, while it operates in the saturation region at the maximum value I_L,max of load current. In this case the approximate expressions of these three poles are given by:

${{p}_{d}}\approx -\frac{1}{{{r}_{o6}}\quad({{g}_{m,P}}\quad{{R}_{O}}{{C}_{gd,P}}\quad+{{C}_{G,P}}\quad)+{{R}_{O}}{{C}_{O}}}$               (8)

${{p}_{nd}}\approx -\frac{{{r}_{o6}}\quad({{g}_{m,P}}\quad{{R}_{O}}{{C}_{gd,P}}+{{C}_{G,P}})\quad+{{R}_{O}}{{C}_{O}}}{{{R}_{o6}}\quad{{R}_{O}}({{C}_{gd,P}}\quad+{{C}_{G,P}}\quad){{C}_{O}}}$              (9)

${{p}_{3}}\approx -\frac{1}{{{R}_{O1,EA}}\quad{{C}_{O1,EA}}}$                (10)

where, C_G,P=C_O2,EA+C_gd,P and C_O=C_L+C_db,P. C_O1,EA and C_O2,EA represent the output capacitances of EA first stage and EA second stage, respectively. C_gd,P, C_gs,P and C_db,P represent the parasitic capacitances gate-to-drain, gate-to-source and drain-to-bulk of the pass transistor M_P.

5a.png

(a) Bode plan location

5b.png

(b) complex s plan location

Figure 5. Pole-zero location with load current variation

Figure 5 shows the dependence of zeros and poles location on the load current I_L in the Bode plan and in the complex s plane, respectively. The frequency location is presented in term of angular frequency ω, where ω_zRHP=z_RHP, ω_pd=−ω_pd, ω_pnd=−p_nd and ω₃=−p₃. For low I_L, the RHP zero is located in the middle frequencies, which introduces a phase shift of −90°, this pushes the non-dominant pole towards the low frequencies, before the unity gain angular frequency ω_UGF. Therefore the magnitude curve in the Bode diagram intersects the frequency axis by a slope of −40 dB/decade and consequently the LDO regulator is unstable. For a case of the large load current, the RHP zero is pushed in the high frequencies, the non-dominant pole is located after the unity gain frequency, so the phase margin is positive but insufficient (less than 45°) to stabilize closed loop response of the LDO regulator system.

It is clear that to stabilize the LDO regulator, it is necessary to separate the dominant and non-dominant poles while keeping a phase margin greater than 45 degree for the entire load current range required by the specifications and keeping higher the unity gain frequency to have a fast transient response, this is achieved by adding a LHP zeros well placed with respect to the non-dominant pole and unity gain frequency locations.

3.2.2 Compensated frequency response

To stabilize the proposed three stage LDO regulator, a dual compensation circuit has been inserted between the LDO output and the pass transistor gate. The compensation network is given by Figure 6. It is composed of two differentiator-current amplifier blocks, (C_C1, R_C1, M₇, M₈) and (C_C2, R_C2, M₉, M₁₀), whose role is to separate the dominant pole from the first non-dominant pole and to create LHP zeros to increase the phase margin. The proposed compensation block has no effect on the elimination of the RHP zero. The compensation circuit requires a symmetrical bias current I_B,C. The cascode trasistors M_7c, M_8c and M_13c help to minimize the effect of channel length modulation to improve matching performance.

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Figure 6. Transistor MOS implementation of proposed frequency compensation circuit

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Figure 7. Small signal model of LDO regulator with proposed compensation circuit

To determine the open loop transfer function H_ol,c(s) of the compensated system, the small-signal equivalent model was made as shown in Figure 7. By application of Kirchhoff's current law and after some mathematical manipulations and some justified simplifications, we find that H_ol,c(s) can be expressed as:

$\begin{align}  & {{H}_{ol,c}}(s)\approx \frac{{{H}_{0,c}}.(1+\frac{s}{{{z}_{RHP}}})(1-\frac{s}{{{z}_{1}}})(1-\frac{s}{{{z}_{2}}})}{(1-\frac{s}{{{p}_{d}}})(1+\frac{{{a}_{2}}}{{{a}_{1}}}s+\frac{{{a}_{3}}}{{{a}_{1}}}{{s}^{2}})(1+\frac{{{a}_{4}}}{{{a}_{3}}}s)(1-\frac{s}{{{p}_{5}}})} \\ \end{align}$               (11)

where,

${{H}_{0,c}}=-\beta {{g}_{m1}}{{g}_{m3}}{{g}_{m,P}}{{R}_{O1,EA}}{{R}_{G,P}}{{R}_{O}}$                 (12)

${{R}_{G,P}}={{r}_{o6}}//{{r}_{o10}}//({{g}_{m8}}r_{o8}^{2})$                    (13)

${{z}_{1}}\approx -\frac{1}{{{R}_{C}}{{C}_{C}}}$                 (14)

${{z}_{2}}\approx -\frac{4}{{{R}_{C}}{{C}_{C}}}$              (15)

${{p}_{d}}\approx -\frac{4}{{{R}_{G,P}}\quad{{g}_{m,P}}\quad{{R}_{O}}[({{g}_{m10}}\quad+{{g}_{m8}}\quad){{R}_{C}}{{C}_{C}}+{{C}_{gd,P}}\quad]}$                 (16)

${{a}_{1}}\approx \frac{{{R}_{G,P}}\quad{{g}_{m,P}}\quad{{R}_{O}}[({{g}_{m10}}\quad+{{g}_{m8}}\quad){{R}_{C}}{{C}_{C}}+{{C}_{gd,P}}\quad]}{4}$                             (17)

$\begin{align}  & {{a}_{2}}\approx \frac{R_{C}^{2}C_{C}^{2}}{4}+{{R}_{G,P}}{{C}_{G,P}}{{R}_{O}}({{C}_{O}}+{{C}_{C,tot}}+{{C}_{gd,P}}) +\frac{{{R}_{C}}{{C}_{C}}}{2}[{{R}_{G,P}}{{C}_{G,P}}+{{R}_{O}}({{C}_{O}}+{{C}_{C,tot}}+{{C}_{gd,P}})] \\ \end{align}$                  (18)

$\begin{align}  & {{a}_{3}}\approx \frac{R_{C}^{2}C_{C}^{2}}{4}[{{R}_{G,P}}{{C}_{G,P}}+{{R}_{O}}({{C}_{O}}+{{C}_{C,tot}}+{{C}_{gd,P}})]\mathop{{}}_{{}}^{{}}+{{R}_{G,P}}{{C}_{G,P}}{{R}_{O}}({{C}_{O}}+{{C}_{C,tot}}+{{C}_{gd,P}})\frac{{{R}_{C}}{{C}_{C}}}{2} \\ \end{align}$                (19)

$\begin{align}  & {{a}_{4}}\approx  \frac{R_{C}^{2}C_{C}^{2}}{4}(\frac{{{C}_{i1}}}{{{g}_{m7}}}+\frac{{{C}_{i2}}}{{{g}_{m9}}}){{R}_{G,P}}{{C}_{G,P}}+\frac{R_{C}^{2}C_{C}^{2}}{4}(\frac{{{C}_{i1}}}{{{g}_{m7}}}+\frac{{{C}_{i2}}}{{{g}_{m9}}}){{R}_{O}}({{C}_{O}}+{{C}_{C,tot}}+{{C}_{gd,P}})]  +\frac{R_{C}^{2}C_{C}^{2}}{4}{{R}_{G,P}}{{C}_{G,P}}{{R}_{O}}({{C}_{O}}+{{C}_{C,tot}}+{{C}_{gd,P}}) \\ \end{align}$                     (20)

${{p}_{5}}\approx -\frac{1}{{{R}_{O1,EA}}\quad{{C}_{O1,EA}}}$                 (21)

H_0,c represents the DC gain of compensated LDO whose value is very close to the value of H_0,u previously expressed by Eq. (3). R_G,P is the total equivalent resistance connected between the gate node of M_p and ground. It also includes the output resistances of the two current amplifiers of the compensation circuit as shown by its expression given by Eq. (13). In the term a₁, gm₈ and gm₁₀ represent the transconductances of the amplifying transistors M₈ and M₁₀ of the compensation circuit, respectively. In the term a₄, g_m7 and C_i1 represent the transconductance of M₇ and the equivalent input capacitor of differentiator-current amplifier (C_C1, R_C1, M₇, M₈) in compensation circuit. Likewise, g_m9 and C_i2 represent the transconductance of M₉ and the equivalent input capacitor of differentiator-current amplifier (C_C2, R_C2, M₉, M₁₀). 

The dominant pole p_d is located at the gate of M_P. z₁ and z₂ are the LHP zeros created by the compensation circuit, where RC represent the compensation resistance such as R_C1=R_C2=RC and C_C is the compensation capacitance such as C_C1=C_C2=C_C. The analysis shows that the non-dominant pole corresponds to two complex conjugate poles which are the roots of the polynomial equation presented in the denominator of Eq. (11). The two complex conjugate poles p₂ and p₃ are given by Eq. (22), where ω₀ is the corner angular frequency given by Eq. (23) and ζ represents the damping factor expressed by Eq. (24). When I_L continues to increase, the quality factor Q=1/(2ζ) increases, and the resonance phenomenon appears in the vicinity of the angular frequency ω₀, whose resonant angular frequency, noted ω_r, is expressed by Eq. (25). The fourth pole is given by p₄=−(a₃/a₄), while the fifth pole p₅ is located at the output node of the error amplifier first stage. Note that the factorization of the numerator and the denominator of the transfer function was done by the method of time constants described in [30].

${{p}_{2,3}}=-\zeta .\omega \pm j{{\omega }_{0}}\sqrt{1-{{\zeta }^{2}}}$             (22)

${{\omega }_{0}}=\sqrt{\frac{{{a}_{1}}}{{{a}_{3}}}}$                  (23)

$\zeta =\frac{{{a}_{2}}{{\omega }_{0}}}{2{{a}_{1}}}$             (24)

${{\omega }_{r}}={{\omega }_{0}}.\sqrt{1-2{{\zeta }^{2}}}$            (25)

As shown in Figure 8, the location of the poles and the RHP zero of the compensated frequency response for proposed LDO changes relatively with load current I_L. Figure 8 shows that the transfer function corresponding to the frequency response of the proposed compensated LDO also contains two other LHP poles p₆ and p₇ and two other LHP zeros z₃ and z₄. In the case of the low load current, zero z₃ cancels pole p₆ and zero z₄ cancels pole p₇. Furthermore, the stability analysis shows that for certain low values of I_L, the two complex conjugate poles move towards the right half-plane. Not shown in this paper, Cardan's method [31], allows to solve a cubic equation whose solutions give the poles p_2,i and p_3,i represented in Figure 8. To avoid this potential instability, the gate width Wp of the pass transistor Mp must meet the condition given by constraint (26), where C_O=C_L+C_db,P and C_C,tot=2C_C. C_gs,ov and C_gd,ov represent the overloop capacitance gate-to-source and gate-to-drain of M_P, respectively [29].

${{W}_{P}}\ge \frac{{{C}_{O}}+{{C}_{C,tot}}}{20{{C}_{gs,ov}}-{{C}_{gd,ov}}}$                    (26)

For the process used in the proposed design, C_gd,ov=C_gs,ov=330 pF/m. Generally C_L=100 pF and therefore we can neglect C_db,P in front of C_L, hence C_O≈C_L. If we choose C_C=1 pF, we find W_P≥16586,9 μm. In conventional LDO design, the minimum value of W_P is given by Eq. (27) [10], where I_L,max is the maximum output current supplied by an LDO regulator to the load, V_DO is the maximum dropout voltage and K_p’ represents a process transconductance parameter of PMOS transistor which is equal in technology used to 96.6 μA/V². For our design specifications, V_DO,max=150 mV and I_L,max=150 mA. If the M_P gate length L_P is set to its minimum value of 0.18-μm, W_P,min=12422,36 μm. We observe that the minimum value of W_P given by Eq. (26) in proposed design, is greater than that given by Eq. (27) in conventional design. Thus, there is a compromise between the layout area occupied by M_P and the stability of the proposed LDO regulator system.

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Figure 8. Pole-zero location in complex s plane for the proposed compensated LDO regulator

$\left(\frac{W_{P}}{L_{P}}\right)_{\min }=\frac{I_{L, \max }}{K_{p}^{\prime} V_{D O}^{2}}$              (27)

To show the robustness of the proposed compensation circuit, we evaluated the phase margin PM for all required values of the load current. The phase margin of the proposed LDO system is given by:

$\begin{align}  & PM\approx 90{}^\circ -{{\tan }^{-1}}(\frac{{{\omega }_{UGF}}}{{{\omega }_{{{z}_{RHP}}}}})+{{\tan }^{-1}}(\frac{{{\omega }_{UGF}}}{{{\omega }_{{{z}_{1}}}}})+{{\tan }^{-1}}(\frac{{{\omega }_{UGF}}}{{{\omega }_{{{z}_{2}}}}}) \\  & \mathop{{}}^{{}}\mathop{{}}^{{}}\mathop{{}}^{{}}\mathop{{}}^{{}}-{{\tan }^{-1}}(\frac{{{\omega }_{UGF}}}{{{\omega }_{pd}}})-{{\tan }^{-1}}Q(\frac{{{\omega }_{UGF}}}{{{\omega }_{0}}}-\frac{{{\omega }_{0}}}{{{\omega }_{UGF}}}) \\  & \mathop{{}}^{{}}\mathop{{}}^{{}}\mathop{{}}^{{}}\mathop{{}}^{{}}-{{\tan }^{-1}}(\frac{{{\omega }_{UGF}}}{{{\omega }_{p4}}})-{{\tan }^{-1}}(\frac{{{\omega }_{UGF}}}{{{\omega }_{p5}}}) \\ \end{align}$                (28)

To have a sufficient phase margin, it is necessary to place the zero z₁ in the vicinity of the unity gain angular frequency ω_UGF and before the resonance angular frequency ω₀ of the two conjugate complex poles, the second zero z₂ is placed in the vicinity of ω₀. If, for example, we choose f_UGF=1 MHz and f_z1= 1.5f_UGF, from Eq. (15), we will have f_z2= 6.f_UGF and therefore f₀≈f_z2≈6 MHz. In this case, and according to Eq. (28), in the worst case where the positive real zero is displaced in the vicinity of the unity gain frequency, the phase margin obtained is equal to 80°. Therefore, the proposed compensation circuit ensures the stability of the LDO regulator for all required values of the load current which represents the desired result.

Finally, the stability condition on the phase margin PM for the proposed LDO regulator system, given by Eq. (29), allows determining the values of R_C and C_C for the desired value of unity gain frequency f_UGF.

$\begin{align}  & PM\approx 90{}^\circ +{{\tan }^{-1}}(2\pi {{f}_{UGF}}{{R}_{C}}{{C}_{C}}) \\  & \mathop{{}}_{{}}^{{}}\mathop{{}}_{{}}^{{}}\mathop{{}}_{{}}^{{}}+{{\tan }^{-1}}(\frac{\pi {{f}_{UGF}}{{R}_{C}}{{C}_{C}}}{2}) \\ \end{align}$                 (29)

3.3 Transient response analysis

Transient response is the dynamic performance of linear regulator [10]. It can be separated into two parts, one is form load variation, named as load transient response, and the other is from line variation, named as line transient response. A typical LDO regulator transient response to load changes is shown in Figure 9.

For an increase of load current by ΔI_L, the LDO output observes an undershoot ΔV_O, for a response time duration of Δt₁. The loop reacts to this load change and the output voltage settles in a time duration defined by reaction time also known settling time Δt₂. Minimizing Δt₁+Δt₂ is a critical need for digital load applications. The LDO response time Δt₁ depends on undershoot ΔV_O, output capacitance C_O and load current change ΔI_L, and can be expressed as:

$\Delta {{t}_{1}}={{C}_{O}}.\frac{\Delta {{V}_{O}}}{\Delta {{I}_{L}}}$                (30)

The settling time, Δt₂ is determined by the open-loop bandwidth ω_pd of the regulation loop and the slew-rate (SR) at the gate of pass transistor MP and can be written as:

$\Delta {{t}_{2}}=\frac{2\pi }{{{\omega }_{pd}}}+SR$        (31)

with,

$SR={{C}_{G,P}}.\frac{\Delta {{V}_{G,P}}}{{{I}_{SR}}}$                 (32)

where, ΔV_G,P and I_SR represent the voltage change and slewing current at the gate of M_P, and we have ΔV_G,P is proportional to ΔV_O.

The proposed compensation circuit also improves the transient response by increasing the bias current at the gate of the pass transistor M_P via the current amplifier block which amplifies this bias current I_B,C during the transient times of the load current, which allows to minimize the slew-rate and consequently to reduce overshoots and undershoots and also to reduce the settling time.

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Figure 9. Typical LDO Regulator Load Transient Response

3.4 Voltage reference

The LDO regulator proposed in this work also includes the voltage reference, which plays an important role in the accuracy of the feedback voltage V_FB, which is why this voltage reference V_REF must have a precise value and independent of the temperature, the supply voltage and the process of the technology used. The voltage reference designed for the LDO regulator was previously realized and published by the same authors [32]. The value of V_REF is equal to 0.635 V.