Low noise, low power, minimum delay and smaller area are the prime factors in the current VLSI system design. There are many sources for noises that exhibit various types of noise. Noise in digital ICs can be credited to various sources such as PSN due to circuit switching transition, deviations in device parameters due to process changes, crosstalk noise caused by capacitive coupling among neighbouring circuit interconnects, noise due to charge sharing and charge leakage. Reducing noise is an important factor in VLSI design. This work involves the analysis and reduction of switching noise in the inverter based equivalent circuit model in 45 nm technology. Also, aims to minimize the power utilization, area and delay. Further the noise analysis is extended to half adder circuit and ALU. The noise value observed for the proposed circuit is 140 μV whereas it is 33 mV for the existing circuit. The same circuit is implemented in GDI based half adder and 4 bit ALU. The simulation result show that the proposed model has reported low noise compared with the existing methods
ALU, gate diffusion input (GDI), simultaneous switching noise (SSN)
ALU-Arithmetic Logic Unit
CMOS-Complementary Metal Oxide Semiconductor
CPU-Central Processing Unit
EDA-Electronic Design Automation
GDI-Gate Diffusion Input
PSN-Power Supply Noise
PTL-Pass Transistor Logic
RCA-Ripple Carry Adder
SoC-System on Chip
SSN-Simultaneous Switching Noise
VDSM-Very Deep Sub Micrometer
VLSI-Very Large Scale Integration
 Mezhiba AV, Friedman EG. (2004). Scaling trends of on-chip power distribution noise. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12(4): 386-394. https://doi.org/10.1109/tvlsi.2004.825834
 Wang CL, Tao YG, Yang P, Liu ZJ. (2017). Dimension reduction and feedback stabilization for max-plus linear systems and applications in VLSI array processors. IEEE 17
Transactions on Automatic Control 62(12): 6353-6368. https://doi.org/10.1109/TAC.2017.2708508ss
 Scotti G, Bellizia D, Trifiletti A, Palumbo G. (2017). Design Of Low-Voltage High-Speed CML D-Latches In Nanometer CMOS technologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25(12): 3509-3520. https://doi.org/10.1109/TVLSI.2017.2750207
 Bait Suwailam MM, Ramahi OM. (2012). Ultrawide-band mitigation of simultaneous switching noise and EMI reduction in high speed PCBs using complementary split ring resonators. IEEE Transactions on Electromagnetic Compatibility 54(2): 389-396. https://doi.org/10.1109/temc.2011.2163940
 Jia YT, Zhang DL, Zhang B. (2015). Slit-surface disturbance lattice ebg structure for simultaneously switching noise suppression in high speed data acquisition system. IEEE Transactions on Components, Packaging and Manufacturing Technology 5(1): 86-98. https://doi.org/10.1109/TCPMT.2014.2376875
 Mandal JK, Mukhopadhyay S. (2012). A novel technique of filtering high random valued impulse noise and optimization through genetic algorithm (HRVINGA). AMSE Journals, France, Series: Advances B 55(1).
 Barik RK, Pradhan M. (2015). Area-time efficient square architecture. AMSE Journals, France, Series Advances D 20(1): 21-34.
 Bikshalu K, Reddy VSK, Reddy PCS, Rao KV. (2014). Electro deposition of nano crystalline La2O3 on p-type Si wafer and electrical characterization for CMOS applications. AMSE Journals, France, Series: Modelling A 87(3): 1-9.
 Seenuvasamurthi S, Nagarajan G. (2017). Power supply noise reduction circuit for mixed signal VLSI systems. International Journal of Digital Signal Processing 9(2): 26-30.
 Seenuvasamurthi S, Nagarajan G. (2017). Power supply noise reduction in mixed signal system on-chip with active decoupling inductor. International Journal of Digital Signal Processing 9(2): 17-25.
 Tapari A, Banerjee B, Viswanathan TR. (2011). CS-CMOS: A low-noise logic family for mixed signal SoCs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19(12): 2141-2148. https://doi.org/10.17577/IJERTV5IS010510
 Seenuvasamurthi S, Nagarajan G. (2016). Highly stable power efficient, noise tolerant circuits for analog and digital systems. IEEE Sponsored, 10th International Conference on Intelligent Systems and Control (ISCO’16), Karpagam College of Engineering, Coimbatore, India (1): 134-139. https://doi.org/10.1109/ISCO.2016.7727040
 Mohammad BS, Saleh H, Ismail M. (2015). Design methodologies for yield enhancement and power efficiency in SRAM based SoCs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23(10): 2054-2064. https://doi.org/10.1109/TVLSI.2014.2360319
 Bhattacharyya P, Kundu B, Ghosh S, Kumar V, Dandapat A. (2015). Performance analysis of a low power, high speed hybrid 1-bit full adder circuit. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23(10): 2001-2008. https://doi.org/10.1109/TVLSI.2014.2357057
 Badaroglu M, Wambacq P, Van der Plas G, Donnay S, Gielen GGE, De Man HJ. (2005). Digital ground bounce reduction by supply current shaping and clock frequency modulation. IEEE Transaction on Computer Aided Design of Integrated Circuits Systems 24(1): 65-76. https://doi.org/10.1109/tcad.2004.839471
 Wang HL, Salman E. (2015). Decoupling capacitor topologies for TSV-based 3-D ICs with power gating. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23(12): 2983-2991. https://doi.org/10.1109/TVLSI.2014.2386253
 Chang NCJ, Hurst PJ, Levy BC, Lewis SH. (2014). Background adaptive cancellation of digital switching noise in a pipelined analog-to-digital converter without noise sensors. IEEE Journal of Solid-State Circuits 49(6): 1397-1407. https://doi.org/10.1109/JSSC.2014.2314446
 Li CF, Chou SC, Ke GH, Huang PC. (2012). A power efficient noise suppression technique using signal-nulled feedback for low-noise wideband amplifiers. IEEE Transactions on Circuits and Systems 59(1): 1-5. https://doi.org/10.1109/tcsii.2011.2177695
 Zhao SY, Roy K, Koh CK. (2002). Decoupling capacitance allocation and its application to power-supply noise-aware floor planning. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 21(1): 81-92. https://doi.org/10.1109/43.974140
 Seenuvasamurthi S, Nagarajan G. (2017). A low noise and power efficient 45nm GPDK technology based highly stable current balancing logic (HCBL) and dynamic logic circuits for mixed signal systems. Association for the Advancement of Modelling and Simulation Techniques in Enterprises (AMSE), France, Series: Advances C 72(1): 11-24, Feb. 2017
 Wang HL, Salman E. (2016). Closed-form expressions for I/O simultaneous switching noise revisited. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25(2): 769-773. https://doi.org/10.1109/TVLSI.2016.2584387
 Morgenshtein A, Fish A, Wagner IA. (2002). Gate-diffusion input (GDI): A power efficient method for digital combinatorial circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10(5): 566-581. https://doi.org/10.1109/TVLSI.2002.801578
 Chandra N, Yati AK, Bhattacharyya AB. (2009). Extended-sakurai-newton MOSFET model for ultra-deep-submicrometer CMOS digital design. 22nd International Conference on VLSI Design, New Delhi, India: 247-252. https://doi.org/10.1109/VLSI.Design.2009.48