A High-Frequency Inductor-Less Chua's Chaotic Oscillator Using Voltage Differencing Current Conveyors

Modern applications such as communication systems, the Internet of Things (IoT), biomedical instrumentation, and cryptography continue to push the demand for compact electronic systems that combine high speed with low power consumption. Meeting these requirements creates difficulties in preserving signal integrity, unpredictability, and security, particularly within non-linear circuits [1]. Chaotic circuits stand out among non-linear circuits as a promising option because of their intricate dynamics and strong sensitivity to initial conditions. Although chaotic circuits obey deterministic equations, their behavior is complex and hard to predict [2, 3]. This distinctive property has turned chaos theory into an active research topic across numerous scientific and engineering fields. Practical uses of chaos have emerged over the years in areas such as secure communication systems, random number generation, biomedical signal processing, and hardware-level encryption [4-6]. Among the chaotic circuits investigated so far, Chua's circuit occupies a prominent position owing to its simple structure and its capacity to produce rich dynamical behavior, including bifurcations and double-scroll attractors [7-9]. As electronic devices evolve toward faster, smaller, and more secure implementations, chaotic circuits that are compact and able to run at higher frequencies are increasingly required. Classical realizations of Chua's circuit, despite their historical importance, often face bandwidth restrictions along with limitations related to component count, power efficiency, and integration feasibility [10-12]. Such constraints become especially critical in emerging areas such as edge computing, secure analog front-ends, and low-power IoT nodes.

To overcome these obstacles, several active devices have been investigated, including operational transconductance amplifiers (OTAs), current feedback operational amplifiers (CFOAs), and second-generation current conveyors. Nevertheless, many of these solutions remain unsatisfactory in terms of frequency scalability or structural simplicity. A Chua's circuit based on the voltage differencing transconductance amplifier (VDTA) is described in the study [13], but it does not provide an inductor-less realization and reaches only a 20MHz operating frequency. The voltage differencing gain amplifier (VDGA) implementation in the study [14] attains a maximum frequency of 21.1MHz. A design employing the extended x second-generation current controlled current conveyor (EXCCCII) in 0.25 µm CMOS technology operates at a comparatively low frequency with a 2.5V supply [15]. The realization in the study [16] adopts the Current Conveyor Transconductance Amplifier (CCTA) and reaches 37.5 MHz, yet it is not an inductor-less design. A low-power version based on the Dual-X Second-generation Current Conveyor (DXCCII) is reported in the study [17]; although inductor-less, it works only in the kHz range. The voltage differencing current conveyor (VDCC) is a comparatively underexplored analog building block that has attracted interest for its wide bandwidth, high linearity, and suitability for current-mode processing [18].

Even with these advantages, no design reported so far in the available literature has employed VDCCs to construct chaotic oscillators, to the best of the authors' knowledge. Unlike related building blocks such as the VDTA [13] or VDGA [14], which require external inductors or additional active stages for signal feedback, the VDCC combines transconductance inputs with a current conveyor core. This allows the synthesis of both the nonlinear diode and the synthetic inductor using only two active blocks. In addition, most published inductor-less realizations of Chua's circuit rely on more than two active blocks, which raises circuit complexity. The design presented here closes this research gap by realizing an inductor-less Chua's circuit with only two VDCC blocks, achieving a record operating frequency of 44.4 MHz while keeping the structure simple and compact. Chua's diode, the essential nonlinear element responsible for the chaotic dynamics, is realized as a new circuit built from a single VDCC. A simulated inductor constructed with the second VDCC completes the design, yielding a minimal yet effective configuration. The achieved operating frequency of 44.4 MHz substantially widens the usable bandwidth relative to most published designs.

The main contributions of this paper are outlined as follows:

1. A new circuit realization of the nonlinear resistors NR₁ and NR₂, together with a novel implementation of Chua's diode based on a single VDCC.

2. A fully active, high-frequency Chua's chaotic oscillator constructed with only two VDCCs.

3. An inductor-less version of the chaotic oscillator obtained through a VDCC-based simulated inductor.

4. Complete mathematical derivations and calculations that clarify the theoretical parameters of the proposed circuit and its sub-circuits.

5. A maximum operating frequency of 44.4 MHz, which makes the design attractive for fast analog and communication systems.

6. An in-depth analysis of how the non-ideal behavior of the VDCC affects the proposed chaotic oscillator.

Developed by Leon O. Chua in 1983, the standard Chua circuit of Figure 1(a) is among the most widely recognized chaotic circuit models. Chaotic behavior requires the circuit to contain three kinds of elements: (i) at least one nonlinear element, (ii) at least one locally active resistor, and (iii) at least three energy storage elements [10]. The appeal of Chua's circuit lies in the wide variety of attractors it can display, ranging from small limit cycles to long-period orbits [22]. As shown in Figure 1(a), the standard circuit comprises one non-linear negative resistor (NR), one inductor (L), two capacitors (C₁ and C₂), and one variable resistor (R_var). The NR, commonly called the Chua diode, is central to the non-linear behavior of the circuit. Figure 1(b) presents the five-segment piecewise-linear I-V characteristic of the Chua diode, illustrating its piecewise-linear negative-resistance property. Conventionally, Chua's diode has been formed by combining two voltage-dependent negative resistors [1]. Chaotic oscillators have received considerable attention because of their roles in secure communications, random number generation, and nonlinear dynamics. Conventional Chua circuit designs, although functional, are constrained by a limited frequency range and inefficient use of components. Progress in active elements, especially the VDCC, opens new possibilities for improving circuit performance. This paper proposes a high-efficiency VDCC-based Chua's circuit that addresses these limitations, and the approach is compared with existing methods to highlight gains in frequency performance, power efficiency, and component count.

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Figure 1. Standard Chua circuit (a) circuit diagram and (b) I-V characteristics

Because the proposed Chua circuit adopts VDCC ABBs as the active elements, this section begins with an overview of the VDCC. The nonlinear resistors, NR₁ and NR₂, are then described, followed by Chua's diode, which governs the nonlinear behavior of the chaotic oscillator. The final subsection presents the simulated inductor circuit that replaces a bulky physical inductor in Chua's circuit.

3.1 Voltage differencing current conveyor

The VDCC is a five-terminal ABB, and its electrical symbol appears in Figure 2(a). Terminals P and N act as high-impedance inputs, terminals Z and W serve as high-impedance outputs, and terminal X operates as a low-impedance output. The voltage and current relationships among these terminals are summarized in Eq. (1).

$\begin{gathered}I_P=I_N=0 \\ I_z=g_m\left(V_P-V_N\right) \\ V_X=V_Z \\ I_{W+}= \pm I_X\end{gathered}$   (1)

Eq. (1) leads to the following observations: the currents entering the P and N terminals are zero because of their high impedance; the current at the Z terminal equals the transconductance gain (g_m) multiplied by the differential input voltage (V_P-V_N); the voltage at the Z terminal is conveyed to the X terminal; and the current at the X terminal is conveyed to the W terminal. Figure 2(b) shows one possible VDCC implementation based on the ICs MAX435 and AD844, while Figure 2(c) presents a CMOS schematic of the VDCC. Both implementations are used later in the simulations of the proposed circuits.

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Figure 2. Voltage differencing current conveyor (VDCC), (a) an electrical symbol, (b) implementation using ICs and (c) a CMOS schematic

3.2 Chua's diode using voltage differencing current conveyor

Chua's diode is a non-linear negative resistance (NR) exhibiting negative piecewise-linear characteristics. Its implementation typically requires two NRs (NR₁ and NR₂). Accordingly, the designs of NR₁ and NR₂ are presented first, followed by the design of the NR itself.

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Figure 3. Design of negative resistances, Chua diode, and simulated inductor using voltage differencing current conveyor (VDCC): (a) NR₁, (b) NR₂, (c) Chua diode and (d) simulated inductor

Design of NR₁: Figure 3(a) shows NR₁ realized with a single VDCC and one resistor. For given values of transconductance (g_m) and resistance (R₁), the theoretical inner slope (m₁₁), outer slope (m₀₁), and breakpoints (V_BP) of NR₁ can be predicted from their analytical expressions, which are derived as follows.

Applying KCL at node A in Figure 3(a) and invoking the VDCC terminal relationship in Eq. (1) yields the inner slope (m₁₁) as:

$m_{11}=\frac{I_{i n}}{V_{i n}}=-g_m$   (2)

The input current $I_{\text {in}}$ of Figure 3(a) can be expressed when VDCC operates in the saturation region as:

$I_{i n}=\frac{V_{i n}-V_Z}{R_A}=\frac{V_{i n}}{R_A}-\frac{V_Z}{R_A}=\frac{V_{i n}}{R_A}-\frac{ \pm V_{s a t}}{R_A}$   (3)

Here, it can be observed that Eq. (3) represents the equation of straight lines in the outer region having a slope of $m_{01}$.

Hence, $m_{01}=\frac{1}{R_A}$   (4)

Applying KVL to Figure 3(a) then gives the breakpoint at the boundary of the saturation regions as:

$\pm V_{B P 1}=\frac{ \pm V_{s a t}}{1+g_m R_A}$   (5)

The resistor R_A of NR₁ is omitted in the proposed Chua's diode design, i.e., R_A = 0 (short circuit), because one of the NRs in Chua's diode always remains in the linear region.

For $R_A=0$, the Outer Slope $\left(m_{01}\right)$ and Breakpoint $\left( \pm V_{B P 1}\right)$, given in Eqs. (4) and (5), respectively, can be expressed as: $m_{01} \approx$ $\infty$ and $\pm V_{B P 1}= \pm V_{\text {sat}}$.

Design of NR₂: Figure 3(b) depicts NR₂ constructed from one VDCC and two resistors. The theoretical expressions for the inner slope (m₁₂), outer slope (m₀₂), and breakpoints (V_BP) of NR₂ for given values of transconductance (g_m) and resistances (R₁ and R₂) are derived below.

Applying KCL at node B in Figure 3(b) together with the VDCC terminal relationship in Eq. (1) gives the inner slope of NR₂ (m₁₂) as:

$m_{12}=\frac{I_{i n}}{V_{i n}}=\frac{-1}{R_2}$   (6)

The input current $I_{\text {in}}$ of Figure 3(b) can be expressed when VDCC operates in the saturation region as:

$I_{i n}=\frac{V_{i n}-V_w}{R_2}=\frac{V_{i n}}{R_2}-\frac{V_w}{R_2}=\frac{V_{i n}}{R_2}-\frac{ \pm V_{s a t}}{R_2}$   (7)

Here, it can be observed that Eq. (7) represents the equation of straight lines in the outer region having a slope of m₀₂.

$m_{02}=\frac{1}{R_A}$   (8)

Applying KVL to Figure 3(b) and rearranging the resulting equation at the boundary of the saturation regions yields the breakpoint of NR₂ as:

$\pm V_{B P 2}=\frac{ \pm V_{\text {sat }}}{1+\frac{R_2}{R_1}}$   (9)

Design of Chua diode/NR: A new non-linear Chua's diode is now obtained by suitably combining NR₁ and NR₂, as illustrated in Figure 3(c).

Applying KCL at node B in Figure 3(c) and using the VDCC terminal relationship in Eq. (1), the inner slope (m₁) of the proposed Chua diode becomes:

$m_1=\frac{I_{i n}}{V_{i n}}=-g_m-\frac{1}{R_2}=m_{11}+m_{12}$   (10)

Similarly, the input current I_in of Figure 3(c) within the saturation region takes the form:

$I_{i n}=\left(-g_m+\frac{1}{R_2}\right) V_{i n}-\frac{ \pm V_{s a t}}{R_2}$   (11)

Here, it can be observed that Eq. (11) is the equation of a straight line having an outer slope of $m_o$.

$m_o=-g_m+\frac{1}{R_2}$   (12)

Combining Eqs. (2), (8), and (12), the outer slope of Chua's diode becomes:

$m_o=m_{11}+m_{o 2}$   (13)

Design of a grounded simulated inductor: Figure 3(d) presents a grounded simulated inductor built from a single VDCC together with one grounded resistor and one grounded capacitor. Routine analysis of Figure 3(d) gives the input impedance (Z_in) of the circuit as:

$Z_{\text {in }}=\frac{V_{\text {in}}}{I_{\text {in}}}=\frac{s R_3 C_3}{g_m}$   (14)

Eq. (14) then gives the equivalent inductance (L_eq) of the circuit as:

$Z_{\text {in }}=\frac{V_{\text {in}}}{I_{\text {in}}}=\frac{s R_3 C_3}{g_m}$   (15)

3.3 Design of Chua's circuit

The standard Chua's circuit of Figure 1(a) is realized here with VDCCs, and the resulting VDCC-based circuit appears in Figure 4. It employs the proposed VDCC-based Chua's diode of Figure 3(c) together with the VDCC-based grounded simulated inductor of Figure 3(d). A variable resistor, R_var, tunes the circuit to produce different attractors. The chaotic outputs consist of the voltage signals V_C1 and V_C2 and the current signal i_L. Notably, the inductor current, i_L, is available at a separate terminal X of VDCC-2.

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Figure 4. Proposed Chua's chaotic circuit using voltage differencing current conveyor (VDCC)

This section examines how the non-ideal characteristics of the active element influence the performance of the proposed Chua's circuit. Since the VDCC serves as the active element, the consequences of its non-idealities deserve careful attention. Two main sources of non-ideality are considered: gain errors and parasitic impedances at the various ports of the VDCC.

5.1 Non-ideality due to gain errors

Gain errors appear in the transconductance gain, voltage gain, and current gain of the VDCC. Their coefficients are denoted α for the voltage gain, β for the transconductance gain, and γ for the current gain, each ideally equal to unity. Including these non-idealities transforms the VDCC port relationship of Eq. (1) into:

$\begin{gathered}I_P=I_N=0 ; I_z=\beta_1 g_m\left(V_P-V_N\right) ; \\ V_X=\alpha V_Z ; I_{W \pm}= \pm \gamma I_X\end{gathered}$   (16)

The analysis now turns to Chua's diode, the central element of Chua's circuit, and to the simulated inductor. To evaluate the effect of the various gain errors on the proposed circuit, Chua's diode and the simulated inductor are analyzed with the modified VDCC port relationship given in (16). Routine analysis of the diode in Figure 3(c) produces the modified inner slope m_1(NI), outer slope m_0(NI), and breakpoints V_BP1(NI), which are stated in Eqs. (17)–(19), respectively.

Innerslope:

$m_{1(N I)}=-\beta_1 g_m-\frac{\alpha \gamma}{R_1}$   (17)

Outerslope:

$m_{o(N I)}=-\beta_1 g_m+\frac{1}{R_2}$   (18)

Breakpoints:

$\pm V_{B P 1}= \pm V_{s a t} ; \pm V_{B P 2}=\frac{\pm V_{s a t}}{1+\frac{\alpha \gamma R_2}{R_1}}$   (19)

Inspection of Eqs. (17)–(19) shows that the gain errors introduce noticeable deviations in the parameters of Chua's diode. By applying linearized nodal analysis around the origin, the resulting characteristic equation becomes:

$\begin{gathered}s^3 C_1 C_2 L_{e q}+s^2\binom{C_1 L_{e q} G_{v a r}+}{C_2 L_{e q}\left(G_{v a r}+m_1(N I)\right)} \\ +s\left(L_{e q} G_{v a r} m_1(N I)+C_1+C_2\right)+G_{v a r}+m_1(N I)=0\end{gathered}$

where, $G_{v a r}=1 / R_{v a r}$ and $m_1(N I)=-\beta_1 g_m-\frac{\alpha \gamma}{R_2}$. This shows that deviations in $\alpha, \beta, \gamma$ slightly shift the condition of oscillation and the frequency of oscillation, but can be easily compensated for in practice by adjusting $R_{\text {var}}$.

As a result, the Condition of Oscillation (CO) and the Frequency of Oscillation (FO) of the circuit are also influenced. These deviations remain small, however, because the simulated values of α, β, and γ are close to unity.

The gain errors are additionally frequency-dependent, and the high-frequency operation of Chua's circuit requires these frequency-dependent effects to be considered. Using a single-pole model, the VDCC gain errors, α(s), β(s), and γ(s), are defined as:

$\alpha(s)=\frac{\alpha_0}{1+\frac{s}{\omega_\alpha}} ; \beta(s)=\frac{\beta_0}{1+\frac{s}{\omega_\beta}} ; \beta(s)=\frac{\gamma_0}{1+\frac{s}{\omega_\gamma}}$   (20)

Here, α₀, β₀, and γ₀ denote the DC gain errors, while ωα, ωβ, and ωγ are the corresponding first-order pole frequencies, whose practical values depend on the internal architecture of the VDCC.

5.2 Non-ideality due to parasitic impedances of voltage differencing current conveyor

The second non-ideality arises from parasitic impedances at the various ports of the VDCC, as illustrated in Figure 12(a). These parasitics can alter the behavior of both Chua's diode and the simulated inductor, and hence of the overall proposed circuit. Figure 12(b) shows Chua's diode with the parasitic impedances included.

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Figure 12. Presence of parasitic impedances on (a) voltage differencing current conveyor (VDCC) and (b) proposed Chua diode

To quantify the influence of the parasitic impedances on Chua's diode, expressions for its inner slope, outer slope, and breakpoints in the presence of parasitics are derived as follows:

By the routine analysis of Figure 12(b), the inner slope $\left(m_{1(P I)}\right)$ and outer slope $\left(m_{o(P I)}\right)$ of the proposed Chua diode, including parasitic, can be expressed as:

$\begin{gathered}m_{1(P I)}=\frac{I_{i n}}{V_{i n}}=-\left(g_m+\frac{1}{R_1+R_X}\right) +\left(\frac{1}{R_P}+S C_P+\frac{1}{R_Z}+S C_z\right) \\ +\frac{\left(\frac{1}{R_1+R_X}+\frac{1}{R_2}\right)\left(\frac{1}{R_W}+S C_W\right)}{\left(\frac{1}{R_2}+\frac{1}{R_W}+S C_W\right)}\end{gathered}$   (21)

$m_{o(P I)}=-g_m+\frac{1}{R_2}+\frac{1}{R_P}+s C_P+\frac{1}{R_Z}+s C_Z$   (22)

The breakpoints, V_BP1 and V_BP2, of the Chua diode with parasitic impedances are similarly obtained as follows:

$\left.\begin{array}{c} \pm V_{B P 1(P I)}= \pm V_{\text {sat }} \\ \pm V_{B P 2(P I)}=\frac{ \pm V_{\text {sat }}}{1+\frac{R_2}{R_1+R_x}}\end{array}\right\}$   (23)

From the expressions of $m_{1(P I)}, m_{0(P I)}, \pm V_{B P 1(P I)}$, and $\pm V_{B P 2(P I)}$, given in Eqs. (21)–(23), respectively, it can be observed that the VDCC-based Chua diode is affected by the parasitic impedances of the VDCC. However, for the simulated values of the parasitic impedance, given in the simulation section, the impacted expressions, given in Eqs. (21)–(23), can be approximated to the real expressions of the inner-slope, outer-slope, and breakpoints of the Chua diode without parasitic impedances.

The proposed Chua circuit is benchmarked against comparable implementations from the existing literature. Several key parameters are examined, including the number of active and passive components, the fabrication technology, the supply voltage, and the highest dominant operating frequency. Table 3 clearly shows the advantage of the proposed design in terms of higher operating frequency, fewer components, and better power efficiency. The dominant operating frequency of 44.4 MHz achieved here is well above the highest value reported in earlier works [17]. The combination of VDCCs and simulated inductors underlies this improvement by extending the frequency range and lowering power consumption. The comparison confirms that the proposed design surpasses state-of-the-art implementations and resolves key limitations such as a narrow frequency range and high power consumption.

Table 3. Comparison with existing Chua circuit implementations

*ABBs: Active Building Blocks; *PCs: Passive Components, *NA: Not Available