A High Gain, Low Power and Low Noise down Conversion Mixer Using 0.18 µm CMOS Process

A High Gain, Low Power and Low Noise down Conversion Mixer Using 0.18 µm CMOS Process

S. S. Rout  K. Sethi 

Department of Electronics & Telecommunication Engineering VSS University of Technology, Burla, Odisha, India

Corresponding Author Email: 
ssrout1988@gmail.com, kabirajsethi@yahoo.com
Page: 
353-367
|
DOI: 
https://doi.org/10.18280/mmc_a.900404
Received: 
17 July 2017
|
Accepted: 
25 July 2017
|
Published: 
31 December 2017
| Citation

OPEN ACCESS

Abstract: 

This paper presents a down conversion mixer design with high gain, low power and low noise. Here, a combination of bulk injection technique, switched biasing technique and current bleeding technique is used for this mixer design. This is simulated in cadence tool using 0.18 µm CMOS process. The bulk injection technique enhances the conversion gain of the mixer with a noisy drain current. This noise is reduced by the use of switched biasing technique with a dc level shifter. The current bleeding technique is used to reduce the effect of parasitic capacitance, which results in progress of conversion gain and also improves the mixer noise. The proposed mixer produces a simulated conversion gain of 11 dB with a noise figure (NF) of about 8.1 dB and the third order input intercept point (IIP3) of 10.8 dBm. The power consumed by the circuit is 0.5 mW from 1.8 V supply voltage.

Keywords: 

Bulk injection, Current bleeding, DC level shifter, Gilbert mixer, Noise figure.

1. Introduction
2. CMOS Mixer Design and Performance Analysis
3. Simulation Results
4. Discussion
5. Conclusion
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