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Twolevel inverters are the most basic kind of multilevel inverter (MLIs). Total harmonic distortion diminishes as the number of output levels is increased. In classic MLI topologies, more electronic components are utilized to get higherlevel outputs, which raises the cost, complexity, and volume of typical MLI installations. By reducing the use of power components, overall costs can be reduced. Further, the two and threelevel inverters produce constant dv/dt output, which increases the stress on the power switches. This research proposed an asymmetric MLI topology that is suitable for PV applications and utilizes a minimum number of components. A selective harmonic eliminationbased pulse width modulation (SHEPWM) is implemented for the proposed inverter to eliminate the lowerorder dominant harmonics. The nonlinear transcendental equations produced by the SHEPWM are solved for the switching angles of the proposed inverter using the NewtonRaphson approach. The performance of the inverter is analyzed based on the THD of output for different operating levels of the inverter. In this research, the NR method yielded a THD of 7.3% at a 0.9 modulation index. Also, the proposed inverter is applied to gridconnected solar PV systems for the analysis of THD.T The THD of the grid voltage is measured as 0.06% and the THD of the grid current is 4.8% with the proposed inverter which is acceptable as per the IEEE519 standards.
THD, optimized inverter, NR method, asymmetric inverter, SHEPWM
Designing mediumvoltage converters for multiple applications such as motor drives, solidstate transformers, and solar photovoltaic presents some common problems such as difficulties with largescale photovoltaic systems, which complicate the converter and control circuit. Multilevel inverter theory was first introduced in 1971 as a substitute for mediumpower applications for a series of connected power electronic switching devices [1]. During the 19711981 era, the MLIs such as neutral point clamped (NPC), a flying capacitor (FC), and cascaded Hbridge (CHB), were suggested [2]. Because of its basic circuit design, the idea of a threelevel NPC converter has become more popular and is still commercially available. However, the rise in levels of neutral point clamped topology considerably increases the number of clamping diodes [3]. The inverse retrieval times of the clamping diode render this topology feasible to develop an inverter with more levels for medium power applications [4]. Hence, the neutral point clamped topology and the flying capacitor topologies are too inadequate for MV and HV applications because they use many condensers requiring prior charging and balancing of the capacitors [56]. Furthermore, a large dclink capacitor needed for singlecell topology limits its application to medium and high voltages, particularly solar PV applications, where different PV panels are connected in series [7]. This vast number of seriesconnected PV panels will decrease the overall system efficiency due to common MPPT and series resistance [89]. Modular structures have been developed by cascading the fullbridge inverters, named multi cell multilevel CHB converter topology, which provides MPPT operation at the module level and is scalable to various voltage levels. Also, clamping diodes and capacitors are not used by CHB topologies [10].
The CHB is getting rid of the more series PV modules; however, continuous module parameters and partial shading will cause mismatch problems [11]. These mismatch problems create imbalance and result in low quality of power to the grid [12]. While using CHB converters for PV applications, this module mismatch is another challenge compared to converters in solidstate transformers and solidstate motor drives. In new industrial and academic research paradigms, multilevel inverters have evolved dramatically because of their ability to produce highquality output at reduced costs. Philosophers have worked on lowering inverter costs by utilizing fewer components. The main aim of a multilevel topology of the inverter is to incorporate the harmonic profile into the IEEE 519 standard, which eliminates the need for heavy filters [13]. Multiple targets such as minimum THD, low dv/dt stress, and lower commonmode voltages are available to guarantee the use of electric motors. Electromagnetic interference (EMI) problems are less frequent on multilevel inverters than on conventional 2level and 3level inverters [14]. In general, researchers aimed at increasing the basic units in series or cascading the basic unit to get more output voltage levels to improve the inverter's efficiency at lower THD [15]. The inverter perceives its usefulness in PVfed UPS, propulsion systems, integration of green energy sources, aero planes, batterypowered vehicles, etc. A simple control strategy is necessary to reduce the complexity of multilevel inverters. Therefore, the investigators focused on efficient topology architecture and modulation [1617].
This paper presented an asymmetric MLI structure with a minimum switch count by avoiding the use of bidirectional switches, clamping diodes, and capacitors in its design. In addition, the proposed converter does not affect diode reverse recovery times, and capacitor voltage balancing and uses a simple gate control circuit due to the absence of bidirectional switches [1820]. A low switching frequency control method is used for the proposed inverter to eliminate the lowerorder harmonics [2122]. A numerical technique, known as the NewtonRaphson method, is used to find a viable solution to the transcendental equations for determining the inverter's optimal switching angles. The proposed inverter is operated for different possible levels (sevenlevel, elevenlevel, fifteen level), and the corresponding THDs are analyzed.
This research presented a simple design topology of an asymmetric inverter suitable to variable dc sources such as SPV systems [23]. The basic cell configuration of the suggested model is given in Figure 1(a). It has a single voltage source in series with a power switch connected across the bypass diode. During the switch 'S' is turned ON, the source voltage 'V' appears at the load, then V_{dcout} becomes source voltage 'V', and while the switch 'S' is turned OFF, then the source voltage is isolated from the load; hence V_{dcout} is '0'.
Figure 1(a). The basic cell configuration
Basic cell structures are cascaded, as shown in Figure 1(b) for 'n' cell structure of the suggested configuration of the inverter, known as the primary circuit.
Figure 1(b). 'n' cell cascaded primary circuit
However, this 'n' cell configuration can generate a multilevel output only with a positive polarity. The bidirectional output of the inverter can be obtained with polarity reversal by connecting an Hbridge auxiliary circuit at the output of the primary circuit, as shown in Figure 1(c).
Figure 1(c). Auxiliary circuit
Therefore, the full cycle of the output's +ve and ve polarity is achieved by combining the primary and auxiliary circuits. This structure synthesizes 15output voltage levels with 7 positive, 7negative, and a zero level using a polarity generator (auxiliary circuit) like the Hbridge module.
Figure 2. Proposed asymmetric inverter topology
The topology of the proposed multilevel inverter for 15level output is shown in Figure 2. In its design, the primary circuit is cascaded with three basic cell structures and interconnected across the auxiliary circuit, which uses three dc sources, seven controlled switches (IGBTs), and 3diodes. The proposed topology and switching path choices are appropriately configured so that IGBTs or diodes can never dead short circuit with the dc sources. The rating of numerous dc sources depends on the magnitude of output levels. The dc source reduced voltage rating specifies V_{dc} step voltage at the output. Different potential dc voltage source combinations are presented in Table 1.
Table 1. Choice of dc sources for suggested topology
Method of Selection 
Choice of DC Sources 
No of Steps 
No of Levels 
Max. O/p Voltage 
Equal Magnitude 
V1=V2=V3=Vdc 
4 
7 
3Vdc 
Unequal Magnitude 
V1=Vdc, V2=V3=2Vdc 
6 
11 
5Vdc 
Binary Approach 
V1=Vdc, V2=2Vdc, V3=4Vdc 
8 
15 
7Vdc 
The binary approach is considered for this study among the above three choices of dc source selection. Since multilevel inverters work with high efficiency at low switching and conduction losses, output voltage levels significantly increase with the minimum number of sources and switching devices. Therefore, the choice of voltages for 15level output is as follows,
V1= Vdc, V2= 2Vdc, V3= 4Vdc
This approach also offers asymmetrical operation to multilevel inverter ideal for variable PV voltages due to variable solar irradiance. The switching sequence for different output step voltages varies from +7 V_{dc} to 7 V_{dc}, including the '0' voltage level.
The switches S_{4} and S_{5} in the auxiliary circuit continuously conduct 7 levels of +ve half cycle of output voltage and switches S_{6} & S_{7} conduct for 7 levels of a ve half cycle of output. The '0' output level is obtained by either a short circuit of load with switches S_{4} & S_{6} ON, or S_{5} & S_{7} ON. Thus, the fifteenlevel output voltage is obtained from the proposed converter by operating the primary and axillary circuits according to the switching conditions described in Table 2.
Table 2. Asymmetric switching sequences and output voltage levels of the proposed 15level inverter
ON Switches 
Power flow path 
Output voltage level 
S1, S2, S3, S4 & S5 
V1+ → S1 → V2 → S2 → V3 → S3 → S4 → Load → S5 → V1 
+7 Vdc 
S2, S3, S4 & S5 
V2+ → S2 → V3 → S3 → S4 → Load → S5 → D1 → V2 
+6 Vdc 
S1, S3, S4 & S5 
V1+ → S1 → D2 → V3 → S3 → S4 → Load → S5 → V1 
+5 Vdc 
S3, S4 & S5 
V3+ → S3 → S4 → Load → S5 → D1 → D2 → V3 
+4 Vdc 
S1, S2, S4 & S5 
V1+ → S1 → V2 → S2 → D3 → S4 →Load → S5 → V1 
+3 Vdc 
S2, S4 & S5 
V2+ → S2 → D3 → S4 → Load → S5 → D1 → V2 
+2 Vdc 
S1, S4 & S5 
V1+ → S1 → D2 → D3 → S4 → Load → S5 → V1 
+ Vdc 
S4 & S6 (or) S5 & S7 
S4 → Load → S6 → S4 (or) S5 → Load → S7 → S5 
0 
S1, S6 & S7 
V1+ → S1 → D2 → D3 → S6 → Load → S7 → V1 
 Vdc 
S2, S6 & S7 
V2+ → S2 → D3 → S6 → Load → S7 → D1 → V2 
2 Vdc 
S1, S2, S6 & S7 
V1+ → S1 → V2 → S2 → D3 → S6 →Load → S7 → V1 
3 Vdc 
S3, S6 & S7 
V3+ → S3 → S6 → Load → S7 → D1 → D2 → V3 
4 Vdc 
S1, S3, S6 & S7 
V1+ → S1 → D2 → V3 → S3 → S6 → Load → S7 → V1 
5 Vdc 
S2, S3, S6 & S7 
V2+ → S2 → V3 → S3 → S6 → Load → S7 → D1 → V2 
6 Vdc 
S1, S2, S3, S6 & S7 
V1+ → S1 → V2 → S2 → V3 → S3 → S6 → Load → S7 → V1 
7 Vdc 
A reduced switch multilevel inverter's main goal is to add levels while using fewer electrical components. Therefore, a number of comparisons between the recommended topology and other cascaded inverters of the same sort were made, including switch count, number of diodes, and dc sources.
Figure 3. Comparison between the existing 15level asymmetric topologies and the proposed 15level inverter
Figure 4. DC sources, switches, diodes & capacitor ratio comparison for other 15level inverters with proposed 15 level inverter
The comparison between the number of dc sources, switches, diodes, and capacitors required for various topologies cited in this thesis with the proposed topology is shown in figure 3. This distinction demonstrates that the suggested topology uses fewer devices in its design. Different components required are presented in Figure 4. Here the Ndc/N and Ns/N are very smaller compared to the other topologies given in the literature. Figure 5 shows the comparison between the number of switches, diodes, and dc sources necessary for the proposed inverter with other topologies.
(a)
(b)
(c)
Figure 5. Comparison between the design components of various MLIs
Selective Harmonic Elimination PWM (SHEPWM) control is one of the best PWM control methods for multilevel converters. Generally, the waveform of multilevel inverter output is expressed using Fourier series expansion. The generalized expression for Fourier series expansion is given in equation (1).
$V(\omega t)=\sum_{n=1}^{\infty} V_n \sin (n \omega t)$ (1)
Here, $\mathrm{V}_{\mathrm{n}}=\mathrm{n}^{\text {th }}$ harmonic voltage magnitude. Due to the odd symmetry of the quarterwave, the evenorder harmonics become zero. Therefore the expression for $\mathrm{V}_{\mathrm{n}}$ becomes,
$V_n=\left\{\begin{array}{l}\frac{4 V_{d c}}{n \pi} \sum_{i=1}^k \cos \left(n \alpha_i\right) ; \text { for odd values of ' } n \text { ' } \\ 0 ; \text { for even values of ' } n \text { ' }\end{array}\right.$ (2)
Where $\alpha_i$ is the switching angles of $\mathrm{i}^{\text {th }}$ harmonic and is between $0^{\circ}90^{\circ}$ (i.e. $0<\alpha_i<\frac{\pi}{2}$ ).
SHEPWM aims to suppress lowerorder harmonics, whereas harmonic filters remove the remaining harmonics. This research developed a 15 level asymmetric inverter with a fundamental switching frequency control scheme to conceal the $5^{\text {th }}, 7^{\text {th }}, 11^{\text {th }}, 13^{\text {th }}, 17^{\text {th }}$, and $19^{\text {th }}$ harmonic voltages. The application of 15 level output will reduce the size of the harmonic filters as the prominent harmonics from the $5^{\text {th }}$ to $19^{\text {th }}$ harmonics are controlled. By expanding equation (2) for odd values of ' $n$ ', equation (3) can be obtained.
$\left.\begin{array}{rl}\frac{4 \mathrm{~V}_{\mathrm{dc}}}{\pi}\left[\cos \alpha_1+\cos \alpha_2+\cdots \ldots+\cos \alpha_7\right] & =\mathrm{V}_1 \\ \frac{4 \mathrm{~V}_{\mathrm{dc}}}{5 \pi}\left[\cos 5 \alpha_1+\cos 5 \alpha_2+\cdots \ldots+\cos 5 \alpha_7\right] & =\mathrm{V}_5 \\ \frac{4 \mathrm{~V}_{\mathrm{dc}}}{7 \pi}\left[\cos 7 \alpha_1+\cos 7 \alpha_2+\cdots \ldots+\cos 7 \alpha_7\right] & =\mathrm{V}_7 \\ \frac{4 \mathrm{~V}_{\mathrm{dc}}}{11 \pi}\left[\cos 11 \alpha_1+\cos 11 \alpha_2+\cdots \ldots+\cos 11 \alpha_7\right] & =\mathrm{V}_{11} \\ \frac{4 \mathrm{~V}_{\mathrm{dc}}}{13 \pi}\left[\cos 13 \alpha_1+\cos 13 \alpha_2+\cdots \ldots+\cos 13 \alpha_7\right] & =\mathrm{V}_{13} \\ \frac{4 \mathrm{~V}_{\mathrm{dc}}}{17 \pi}\left[\cos 17 \alpha_1+\cos 17 \alpha_2+\cdots \ldots+\cos 17 \alpha_7\right] & =\mathrm{V}_{17} \\ \frac{4 \mathrm{~V}_{\mathrm{dc}}}{19 \pi}\left[\cos 19 \alpha_1+\cos 19 \alpha_2+\cdots \ldots+\cos 19 \alpha_7\right] & =\mathrm{V}_{19}\end{array}\right\}$ (3)
Where, $V_5, V_7, V_{11}, V_{13}, V_{17}, V_{19}$ are the harmonic voltages of $5^{\text {th }}, 7^{\text {th }}, 11^{\text {th }}, 13^{\text {th }}, 17^{\text {th }}, 19^{\text {th }}$ harmonics, respectively, which are required to suppress to reduce the $\mathrm{THD}$ of output voltage. Therefore, these are equated to zero, and the resulting equation can be represented in equation (5). The fundamental voltage component in equation (3) is equated to the modulation index corresponding PWM scheme, which can be written as:
$M=\frac{V_1}{V_{1 \max }}$ (4)
Where, $V_{1 \max }=$ Peak fundamental voltage, $V_{1 \max }=\frac{4 k V_{d c}}{\pi}$, $\mathrm{V}_1=$ Actual fundamental voltage, $\mathrm{k}=$ Degree of freedom $=$ $(\mathrm{N}1) / 2, \mathrm{~N}=$ No of output voltage levels
By combining (3) and (4) the above conditions can be written as follows.
$\left.\begin{array}{l}\frac{4 V_{d c}}{\pi}\left(\cos \alpha_1+\cos \alpha_2+\cos \alpha_3+\cos \alpha_4+\cos \alpha_5+\cos \alpha_6+\cos \alpha_7\right)=M \\ \frac{4 V_{d c}}{5 \pi}\left(\cos 5 \alpha_1+\cos 5 \alpha_2+\cos 5 \alpha_3+\cos 5 \alpha_4+\cos 5 \alpha_5+\cos 5 \alpha_6+\cos 5 \alpha_7\right)=0 \\ \frac{4 V_{d c}}{7 \pi}\left(\cos 7 \alpha_1+\cos 7 \alpha_2+\cos 7 \alpha_3+\cos 7 \alpha_4+\cos 7 \alpha_5+\cos 7 \alpha_6+\cos 7 \alpha_7\right)=0 \\ \frac{4 V_{d c}}{11 \pi}\left(\cos 11 \alpha_1+\cos 11 \alpha_2+\cos 11 \alpha_3+\cos 11 \alpha_4+\cos 11 \alpha_5+\cos 11 \alpha_6+\cos 11 \alpha_7\right)=0 \\ \frac{4 V_{d c}}{13 \pi}\left(\cos 13 \alpha_1+\cos 13 \alpha_2+\cos 13 \alpha_3+\cos 13 \alpha_4+\cos 13 \alpha_5+\cos 13 \alpha_6+\cos 13 \alpha_7\right)=0 \\ \frac{4 V_{d c}}{17 \pi}\left(\cos 17 \alpha_1+\cos 17 \alpha_2+\cos 17 \alpha_3+\cos 17 \alpha_4+\cos 17 \alpha_5+\cos 17 \alpha_6+\cos 17 \alpha_7\right)=0 \\ \frac{4 V_{d c}}{19 \pi}\left(\cos 19 \alpha_1+\cos 19 \alpha_2+\cos 19 \alpha_3+\cos 19 \alpha_4+\cos 19 \alpha_5+\cos 19 \alpha_6+\cos 19 \alpha_7\right)=0\end{array}\right\}$ (5)
The switching angles must not violate the constraints,
$\alpha_1<\alpha_2<\alpha_3<\alpha_4<\alpha_5<\alpha_6<\alpha_7<\frac{\pi}{2}$ (6)
The set of nonlinear equations in (5) can be solved using constraint (6) to obtain the switching angles required for the fifteenlevel inverter. These equations can be solved using a fundamental switching frequency control method and optimization methods to optimize the inverter's switching angles. Any optimization strategy requires developing an objective function related to the variables to be evaluated. The primary objectives are,
a. To obtain the value of the base voltage equivalent to any preset or expected value.
b. To suppress or reduce a few harmonics of lower order.
The inverter's switching angles influence the output harmonic voltages. The generalized harmonic voltage objective function (OF) consists of the following form to achieve the above objectives:
$O F=\min _{\alpha_k}\left\{\left(100 \times\left(\frac{V_1^*V_1}{V_1^*}\right)^4\right)+\sum_{k=2}^N \frac{1}{h_k}\left(50 \times \frac{V_{h_k}}{V_1}\right)^2\right\}$ (7)
To minimize the $5^{\text {th }}, 7^{\text {th }}, 11^{\text {th }}, 13^{\text {th }}, 17^{\text {th }}$, and $19^{\text {th }}$ harmonics, the above objective function can be taken as:
$O F=100 \times\left(\frac{V_1^*V_1}{V_1^*}\right)^4+\left(\frac{50}{V_1}\right)^2 \times\left(\frac{V_5^2}{5}+\frac{V_7^2}{7}+\frac{V_{11}^2}{11}+\frac{V_{13}^2}{13}+\frac{V_{17}^2}{17}+\frac{V_{19}^2}{19}\right)$ (8)
Where, $\mathrm{V}_{1 \mathrm{~d}}=$ Desired fundamental voltage, $\mathrm{V}_1$ = Actual fundamental voltage, $V_5=$ Harmonic voltage of $5^{\text {th }}$ Harmonic, $V_7=$ Harmonic voltage of $7^{\text {th }}$ harmonic, $\mathrm{V}_{11}=$ Harmonic voltage of $11^{\text {th }}$ harmonic, $\mathrm{V}_{13}=$ Harmonic voltage of $13^{\text {th }}$ harmonic, $\mathrm{V}_{17}=$ Harmonic voltage of $17^{\text {th }}$ harmonic, $\mathrm{V}_{19}$ = Harmonic voltage of $19^{\text {th }}$ harmonic.
The objective of this research is to minimize the above objective function to reduce THD. The transcendental equations (5), satisfying the constraint function (6) with objective function (8), can be solved by using the NR method for minimum THD and optimal switching angles of the proposed multilevel inverter. The comparison between different switching control methods with the proposed SHEPWM control is given in table. 3 .
Table 3. Comparison between switching control methods with SHEPWM
Method of switching 
SVPM 
SVPWM 
SHEPWM 
Utilization of dc sources 
0~0.866 
0~1 
0~1.12 
Frequency of switching 
Medium 
High 
Low 
Complexity 
Low 
High 
High 
Implementation 
Online 
Online 
Offline 
The seven switching angles for seven switches in the inverter are first computed by the numerical successive approximation technique known as Newton Raphson (NR) approach. The computation of switching angles involves equations (5) with equation (6). The stepbystep procedure followed in the NR method for the solution of nonlinear equations is described below.
Step 1: For the calculation of switching angles, a matrix is formulated with seven (17) switching angles in equation (9)
$\alpha^i=\left[\alpha^1, \alpha^2, \alpha^3, \alpha^4, \alpha^5, \alpha^6, \alpha^7\right]^T$ (9)
Step 2: The nonlinear system matrix is formulated in equation (10), and the transpose matrix of its partial derivation concerning switching angles is given in equation (11)
$F^i=\left[\begin{array}{l}\cos \left(\alpha_1^i\right)+\cos \left(\alpha_2^i\right)+\cos \left(\alpha_3^i\right)+\cos \left(\alpha_4^i\right)+\cos \left(\alpha_5^i\right)+\cos \left(\alpha_6^i\right)+\cos \left(\alpha_7^i\right) \\ \cos \left(5 \alpha_1^i\right)+\cos \left(5 \alpha_2^i\right)+\cos \left(5 \alpha_3^i\right)+\cos \left(5 \alpha_4^i\right)+\cos \left(5 \alpha_5^i\right)+\cos \left(5 \alpha_6^i\right)+\cos \left(5 \alpha_7^i\right) \\ \cos \left(7 \alpha_1^i\right)+\cos \left(7 \alpha_2^i\right)+\cos \left(7 \alpha_3^i\right)+\cos \left(7 \alpha_4^i\right)+\cos \left(7 \alpha_5^i\right)+\cos \left(7 \alpha_6^i\right)+\cos \left(7 \alpha_7^i\right) \\ \cos \left(11 \alpha_1^i\right)+\cos \left(11 \alpha_2^i\right)+\cos \left(11 \alpha_3^i\right)+\cos \left(11 \alpha_4^i\right)+\cos \left(11 \alpha_5^i\right)+\cos \left(11 \alpha_6^i\right)+\cos \left(11 \alpha_7^i\right) \\ \cos \left(13 \alpha_1^i\right)+\cos \left(13 \alpha_2^i\right)+\cos \left(13 \alpha_3^i\right)+\cos \left(13 \alpha_4^i\right)+\cos \left(13 \alpha_5^i\right)+\cos \left(13 \alpha_6^i\right)+\cos \left(13 \alpha_7^i\right) \\ \cos \left(17 \alpha_1^i\right)+\cos \left(17 \alpha_2^i\right)+\cos \left(17 \alpha_3^i\right)+\cos \left(17 \alpha_4^i\right)+\cos \left(17 \alpha_5^i\right)+\cos \left(17 \alpha_6^i\right)+\cos \left(17 \alpha_7^i\right) \\ \cos \left(19 \alpha_1^i\right)+\cos \left(19 \alpha_2^i\right)+\cos \left(19 \alpha_3^i\right)+\cos \left(19 \alpha_4^i\right)+\cos \left(19 \alpha_5^i\right)+\cos \left(19 \alpha_6^i\right)+\cos \left(19 \alpha_7^i\right)\end{array}\right]$ (10)
$\left[\frac{\partial F^i}{\partial a}\right]^T=\left[\begin{array}{l}\sin \left(\alpha_1^i\right)\sin \left(5 \alpha_1^i\right)\sin \left(7 \alpha_1^i\right)\sin \left(11 \alpha_1^i\right)\sin \left(13 \alpha_1^i\right)\sin \left(17 \alpha_1^i\right)\sin \left(19 \alpha_1^i\right) \\ \sin \left(\alpha_2^i\right)\sin \left(5 \alpha_2^i\right)\sin \left(7 \alpha_2^i\right)\sin \left(11 \alpha_2^i\right)\sin \left(13 \alpha_2^i\right)\sin \left(17 \alpha_2^i\right)\sin \left(19 \alpha_2^i\right) \\ \sin \left(\alpha_3^i\right)\sin \left(5 \alpha_3^i\right)\sin \left(7 \alpha_3^i\right)\sin \left(11 \alpha_3^i\right)\sin \left(13 \alpha_3^i\right)\sin \left(17 \alpha_3^i\right)\sin \left(19 \alpha_3^i\right) \\ \sin \left(\alpha_4^i\right)\sin \left(5 \alpha_4^i\right)\sin \left(7 \alpha_4^i\right)\sin \left(11 \alpha_4^i\right)\sin \left(13 \alpha_4^i\right)\sin \left(17 \alpha_4^i\right)\sin \left(19 \alpha_4^i\right) \\ \sin \left(\alpha_5^i\right)\sin \left(5 \alpha_5^i\right)\sin \left(7 \alpha_5^i\right)\sin \left(11 \alpha_5^i\right)\sin \left(13 \alpha_5^i\right)\sin \left(17 \alpha_5^i\right)\sin \left(19 \alpha_5^i\right) \\ \sin \left(\alpha_6^i\right)\sin \left(5 \alpha_6^i\right)\sin \left(7 \alpha_6^i\right)\sin \left(11 \alpha_6^i\right)\sin \left(13 \alpha_6^i\right)\sin \left(17 \alpha_6^i\right)\sin \left(19 \alpha_6^i\right) \\ \sin \left(\alpha_7^i\right)\sin \left(5 \alpha_7^i\right)\sin \left(7 \alpha_7^i\right)\sin \left(11 \alpha_7^i\right)\sin \left(13 \alpha_7^i\right)\sin \left(17 \alpha_7^i\right)\sin \left(19 \alpha_7^i\right)\end{array}\right]$ (11)
Step 3: Formulation of harmonic magnitude matrix and represented in equation (12)
$T=\left[\frac{\pi M_i}{4}, 0,0,0,0,0,0\right]^T$ (12)
Equations (5) and (12) are modified and rewritten as equation (13)
$F(\alpha)=T$ (13)
The matrices (9) to (13) are simulated in MATLAB software for the programmed NR method, which is implemented described in the following steps.
Step 1: Predict the initial switching angles using the equal area criterion with the equation (14)
$\alpha^0=\left[\alpha_1^0, \alpha_2^0, \alpha_3^0, \alpha_4^0, \alpha_5^0, \alpha_6^0, \alpha_7^0\right]$ (14)
Step 2: This step involves the design equations of the NR approach from equations (15) to (18)
$F\left(\alpha^0\right)=F^0$ (15)
The equation (13) is linearized to get the $\alpha^0$
$F^0+\left[\frac{\partial F}{\partial \alpha}\right]^0 d \alpha^0=T$ (16)
And,
$d \alpha^0=\left[d \alpha_1^0, d \alpha_2^0, d \alpha_3^0, d \alpha_4^0, d \alpha_5^0, d \alpha_6^0, d \alpha_7^0\right]$ (17)
Equation (17) can be solved using the inverse of the equation represented in equation (18).
$d \alpha^0=I N V\left[\frac{\partial F}{\partial \alpha}\right]^0\left(TF^0\right)$ (18)
Step 3: Update the initial values using the equation (19)
$\alpha^{i+1}=\alpha^i+d \alpha^i$ (19)
Step $2 \& 3$ are repeated till the $d \alpha^i$ is satisfied for the degree of accuracy and to satisfy the constraint, $\alpha_1<\alpha_2<\alpha_3<$ $\alpha_4<\alpha_5<\alpha_6<\alpha_7<\frac{\pi}{2}$. Thus the switching angles $\alpha_1$ to $\alpha_7$ be evaluated using the Newton Raphson approach, and the same is stored in the lookup tables for different modulation indexes. These switching angles are retrieved from the memory of lookup tables during the realtime operation of the inverter for the required modulation index.
The proposed asymmetric inverter is implemented on MATLAB Simulink using seven IGBT switches, three switched diodes, and three dc sources. To generate the switching pulses, a selective harmonic elimination pulse width modulation has been used. The switching frequency is 50Hz, the maximum harmonic frequency is 1 kHz, and the Nyquist frequency for THD is 5 kHz. The inverter's load is modeled as a nonresistive load with R = 26.83 Ω and L = 9.9 mH. The switching angles are evaluated using SHEPWM at 0.9 modulation index. The proposed inverter can operate at different levels with the choice of dc sources as described below.
6.1 Equal magnitude of dc sources
Considering the input dc sources of the proposed inverter shown in Figure 2 as the ratio of 1:1:1, i.e. all the dc sources with equal magnitude, a sevenlevel output voltage is produced at the inverter output. Here the magnitude of dc sources is taken as V_{1} = 37V, V_{2} = 37V, and V_{3} = 37V to get a peak voltage of 111V. The switching pulses of the sevenlevel operation of the proposed inverter are shown in Figure 6. Figure 7 shows the 7 level output voltage waveform of the proposed inverter with an equal magnitude of dc sources, and Figure 8 shows the corresponding THD of the 7level output of the proposed inverter, which is 15.36%.
(a)
(b)
Figure 6. Switching pulses of proposed inverter for seven level operation. (a) Primary circuit (b) Auxiliary circuit
Figure 7. The 7Level output voltage of the asymmetric inverter
Figure 8. THD of output voltage for 7level operation
6.2 Unequal magnitude of dc sources
Considering the input dc sources of the proposed inverter shown in Figure 2 as the ratio of 1:2:2, i.e. the dc sources with unequal magnitude, an elevenlevel output voltage is produced at the inverter output. Here the magnitude of dc sources is taken as V_{1} = 37V, V_{2} = 74V, and V_{3} = 74V to get a peak voltage of 185V. The switching pulses of eleven level operation of the proposed inverter are shown in Figure 9. Figure 10 shows the 11level output voltage waveform of the proposed inverter with an unequal magnitude of dc sources. Figure 11 shows the corresponding THD of the 11level output of the proposed inverter, which is 11.17%.
(a)
(b)
Figure 9. Switching pulses of proposed inverter for eleven level operation. (a) Primary circuits (b) Auxiliary circuit
Figure 10. The 11level output voltage of the asymmetric inverter
Figure 11. THD of output voltage for 11level operation
6.3 Binary approach of DC sources
Considering the input dc sources of the proposed inverter shown in Figure 2 as the ratio of 1:2:4, i.e. the dc source magnitudes are different from one to another, a fifteenlevel output voltage is produced at the inverter output. Here the magnitude of dc sources is taken as V_{1} = 37V, V_{2} = 74V, and V_{3} = 148V to get a peak voltage of 259V. The switching pulses corresponding to the generated switching angles are shown in Figure 12(a) for the primary circuit and Figure 12(b) for an auxiliary circuit. Figure 13 shows the 15level output voltage waveform of the proposed inverter with the binary approach of dc sources (1:2:4 ratio) Figure 14 shows the load current waveform for 15level operation, and Figure 15 shows the corresponding THD of the 15level output of the proposed inverter, which is 7.3%. Figure 14 confirms that the output current waveform approximately resembles the sinusoidal waveform without using any filter at the output of the inverter. Also, it is in phase with the load voltage so that the power factor is maintained approximately unity.
(a)
(b)
Figure 12. Switching pulses of proposed inverter for 15level operation. (a) Primary circuits (b) Auxiliary circuit
Figure 13. The 15level output voltage of the asymmetric inverter
Figure 14. The 15level output current of asymmetric inverter
Figure 15. THD of the output voltage of the proposed inverter for 15level operation
The detailed comparison of the results of the proposed inverter was compared with the work presented in the literature. Table.4 reveals that the proposed asymmetric inverter utilizes less number of switches compared to the other topologies and also produces less % THD without employing any filter at the output.
The peak value of output voltage is 259V, and the peak value of current is 9.65A for the figures shown in 13 and 14 respectively. To get the RMS values of output voltage and current, the peak values are divided by $\sqrt{2}$. Thus, the RMS value of the output voltage is 183.16V}, and the RMS value of the output current is 6.83A.
Therefore the output power of the 15 level inverter is determined by taking the product of RMS values of output voltage and current.
$\begin{aligned} \mathrm{P}_0 & =\mathrm{V}_{\mathrm{RMS}} * \mathrm{I}_{\mathrm{RMS}} \\ & =183.16 * 6.83 \\ & =1250 \mathrm{~W}\end{aligned}$
Thus the output of the proposed 15level inverter is computed as 1250W.
Table 4. THD comparisons of the proposed inverter with literature work
Author 
Type of Inverter 
No of Sources 
No of Switches 
No of Levels 
Max. O/p Voltage 
%THD 
Jagdish Kumar (2008) 
Symmetric CHB 
5 
20 
11 
5Vdc 
7.9% 
Aman Parkash (2014) 
Symmetric HBridge 
3 
12 
7 
3Vdc 
11.68% 
Faouzi ARMI (2016) 
Symmetric CHB inverter 
4 
16 
9 
4Vdc 
19.3% 
Asymmetric CHB inverter 
3 
12 
7 
3Vdc 
25.91% 

Asymmetric CHB inverter 
3 
12 
9 
4Vdc 
10.2% 

Wahidah Abd Halim (2017) 
Symmetric CHB inverter 
3 
12 
7 
3Vdc 
11.9% 
Asymmetric CHB inverter 
4 
16 
9 
4Vdc 
8.4% 

3 
7 
7 
3Vdc 
15.36% 

Proposed 
Asymmetric modular 
3 
7 
11 
5Vdc 
11.17% 
Multilevel inverter 
3 
7 
15 
7Vdc 
7.30% 
6.4 Application of proposed inverter on gridconnected PV system
Figure 16. Power flow diagram for singlephase grid connected SPV system
Singlephase SPV systems are generally implemented for lowpower applications of the range of a few kilowatts with maximum power point tracking at unity power factor [27]. The SPV system pumps the power into the grid when the output power exceeds the load demand. The active power flow in the gridconnected SPV system depends on the power generated by the SPV system or the power demand of the grid. Figure 16 shows the power flow diagram between the SPV system and grid when the unity power factor is required at the grid side for low and medium power applications.
Asymmetric PV sources feed the input dc supply of the proposed inverter. The current into the grid is injected by using an adaptive PI controller. The nature of the current injected to be sinusoidal and in phase with the grid voltage to maintain the unity power factor. To produce a sinusoidal grid current, the dc voltages provided by the PV array must be kept constant at all times.
There are two different control strategies used for voltage control for injecting the current into the grid. One can control the total dc voltage of the proposed inverter, while the other control the dc voltage of specific dc sources supplied by the PV array. Because asymmetrical PV inputs are connected to the inverter through dc links, individual dcdc boost converters with MPPT controllers are constructed for each PV source in the proposed configuration. Under various operating situations, these independent MPPT controllers keep the dc link voltages in the 1: 2: 4 ratio. To produce the reference PV voltages such as V_{dc1}, V_{dc2,} and V_{dc3} a P&Obased MPPT algorithm is used. The Simulation model diagram is given in Figure 17 for the gridconnected PVbased proposed inverter.
Figure 17. Singlephase gridconnected SPV system with the proposed asymmetric inverter
Figure 18. Grid Voltage and Grid current waveforms
Figure 19. Active & Reactive power delivered by the inverter to the grid
While connecting the proposed asymmetric inverter to the singlephase gridconnected PV system, three different PV sources were considered as shown in Figure 17. The grid voltage and grid current waveforms for the same are given in Figure 18. Also, Figure 19 presents the Active and Reactive power output of the gridconnected PV system with the proposed inverter. Further, the THDs of grid voltage and currents were measured and is given in Figure 20 and Figure 21 respectively.
Figure 20. THD of the Grid voltage waveform
Figure 21. THD of the Grid current waveform
From Figure 20 and Figure 21, it is observed that the THD of the grid voltage is 0.06% and he THD of the grid current is 4.8% respectively, which is less than 5% and highly acceptable according to IEEE519 standards.
An asymmetric 15level inverter with 7switches, 3diodes had been developed in this paper to optimize the size of the design topology. The inverter also operated 7level and 11 level operation with a proper choice of dc source selection. The lower order dominant harmonics in the inverter output had been minimized using a lowfrequency switching modulation (SHEPWM). The transcendental equations generated in SHEPWM had been solved using the Newton Raphson method to obtain the switching angles. The THD of the inverter output had been analyzed for 7level, 11level and 15level operations using equal magnitude, unequal magnitude and binary approaches of dc sources respectively. The fifteenlevel operation had given a minimum of 7.3%, compared to other levels of operation without using filter at the inverter output. Also the proposed inverter is integrated to grid connected solar photovoltaic system, which given the grid voltage is 0.06% and he THD of the grid current is 4.8% respectively which is acceptable according to IEEE519 standard.
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