FPGA Implementation of Arcsine Function Using CORDIC Algorithm

FPGA Implementation of Arcsine Function Using CORDIC Algorithm

Anurup Saha Archisman Ghosh K. Gaurav Kumar 

ADES Lab, Dept. of E.T.C.E, Jadavpur University, Kolkata 700032, India

Corresponding Author Email: 
sahaanurup24@gmail.com, archismanghosh12@gmail.com, kgauravkumar35@gmail.com
Page: 
196-201
|
DOI: 
https://doi.org/10.18280/ama_a.540205
Received: 
25 September 2017
|
Accepted: 
30 September 2017
|
Published: 
30 June 2017
| Citation

OPEN ACCESS

Abstract: 

This paper presents finite state machine based hardware to calculate arcsine function using CORDIC algorithm. CORDIC algorithms provide an effective methodology to compute a large range of transcendental functions, since it only requires addition, shift and subtraction operations.  The design has been done using verilog HDL and it has been tested in SPARTAN-3 FPGA. Since different applications may require different accuracy, the focus has been on how an FPGA implementation of arcsine function can be easily reconfigured when higher precision is required.

Keywords: 

CORDIC, FPGA, Computer arithmetic, Arcsine, ASM.

1. Introduction
2. Cordic Algorithm
3. Steps to Compute Arcsine
4. Results and System Performance
5. Conclusion
Acknowledgment

The authors would like to thank Prof. M. K. Naskar, Asim Maiti for their constant help, guidance, and support.

  References

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