Functionnally Asynchronous VLSI Cellular Array for Morphological Filtering of Images
Un Réseau Cellulaire VLSI Fonctionnellement Asynchrone pour le Filtrage Morphologique D'Images
OPEN ACCESS
The design of a fine grain asynchronous VLSI cellular array is presented. It is shown how asynchronism can be exploited at both functional and structural levels. A joint algorithmic-architectural study has led to the fabrication of an integrated circuit including 16x16 processing elements.The data and control paths are designed using a standard-cell approach, combining CMOS and DCVSL (Differential Cascode Voltage Switch Logic) gates. The 800,000 transistorcircuit enables real time morphological filtering of images.
Résumé
A travers la présentation de la conception d'un réseau cellulaire VLSI asynchrone à grain fin, il est montré comment la notion d'asynchronisme peut être exploitée à la fois au niveau fonctionnel et au niveau architectural. Une étude conjointe algorithme-architecture a abouti à la conception d'un circuit intégrant 16x16 processeurs élémentaires. Le flot de conception des chemins de données et de contrôle est basé sur une approche «cellules standard » qui combine des portes CMOS et DCVSL (DifferentialCascode Voltage Switch Logic). Ce circuit d'environ 800.000 transistors permet de mettre en oeuvreen temps réel des algorithmes itératifs de filtrage morphologique par reconstruction.
asynchronous VLSI circuit, asynchronous algorithm, cellular array, image processing, mathematical morphology.
Mots clés
circuit VLSI asynchrone, algorithme asynchrone, réseau cellulaire, traitement d'images, morphologie mathématique.
[1] K . Batcher, «Design of a Massively Parallel Processor», IEEE Transactions on Computers, vol. C-29, 1980, pp. 836-840.
[2] K. Preston, M. Duff, Modern Cellular Automata, PlenumPress 1984.
[3] G. Privat, P. Planet, M. Renaudin, «Asynchronous relaxation of locallycoupled automata networks, with application to parallel VLSI implementation of iterative image processing algorithms»,Proceedings of the International Conference on Application Specific Array Processors, October 1993.
[4] G.Privat, F. Robin, M. Renaudin, B. El Hassan, «A fine-grain asynchronous VLSI cellular array processor architecture», Proceedings of the International Symposium on Circuits And Systems, Seattle, 1995.
[5] D. Chazan, W. Miranker, «Chaotic relaxation», Linear Algebra and its Applications, vol.2, 1969, pp. 199-222.
[6] G.Baudet,«Asynchronous iterative methods for multiprocessors»,Journal of the Association for Computing Machinery, vol.25, n°2, April 1978, pp. 226244.
[7] A. Üresin, M. Dubois, «Sufficient conditions for the convergence of asynchronous iterations», Parallel Computing, vol. 10, 1989, pp. 83-92.
[8] P. Salembier, J. Serra,«Morphological multiscale image segmentation», ProceedingsSPIEon Visual Communications and Image Processing, vol. 1818, 1992, pp. 620-631.
[9] L. Vincent, «Morphological grayscale reconstruction in image analysis : applications and efficient algorithms»,IEEE Transactions on Image Processing, vol. 2, n°2, April 1993, pp. 176-201.
[10] F. Robin, G. Privat, M. Renaudin, «Asynchronous relaxation of morphological operators : a joint architecture-algorithm perspective», Proceedingsof the International Workshop on Parallel Image Analysis, Lyon, France, December 1995.
[11] B. El Hassan, «Architecture VLSI asynchrone utilisant la logique différentielleà précharge : application aux opérateurs arithmétiques», Ph.D. Thesis, INPG, Grenoble,France, September 1995.
[12] M. Renaudin, B. El Hassan, «The design of fast asynchronous adder structures and their implementation using DCVS logic», Proceedings of the International Symposium on Circuits And Systems, London, 1994.
[13] M. Renaudin, B. El Hassan, «A minimum power, 100 MHz, 12x 18 +30-b Multiplier-Accumulator operating in asynchronous and synchronous mode»,Proceedings of the European Solid-State CIRcuits Conference, Ulm, Germany, September 1994.
[14] B. El Hassan, A. Guyot, M. Renaudin, V. Levering, «New self timed rings and their application to division and square root extraction», Proceedings of the European Solid-State CIRcuits Conference, Lille, France, September 1995, pp. 226-229.
[15] C.H. Erdelyi, W.R. Griffin, R.D. Kilmoyer, « Cascode Voltage Switch Logic Design», VLSI Design,October 1984, pp. 78-86.
[16] M, Renaudin, B. El Hassan, A. Guyot, «A new asynchronous pipeline scheme: application to the design of a self-timed ring divider», IEEE Journalof Solid-State Circuits, vol. 31, n°7, July 1996, pp. 1001-1013.
[17] F. Robin, M. Renaudin, G.Privat,N. Van Den Bossche, «Functionally asynchronous array-processor for morphological filtering of greyscale images», IEE Proceedings on Computers and Digital Techniques, special section on Asynchronous Architecture, vol. 143, n°5, September 1996, pp. 273-281.
[18] L. Kleeman, A. Cantoni, <<Metastable behavior in digital systems», IEEE Design & Test of Computers, December 1987, pp. 4-19.
[19] F.U. Rosenberger, C.E. Molnar, T.J. Chaney, T.P. Fang, «Q-modules : internally clocked delay-insensitive modules», IEEE Transactions on Computers,vol.37, n°9, September 1988.
[20] S. Hauck, «Asynchronous Design Methodologies :An Overview»,Proceedings of the IEEE, vol.83, n° 1, January 1995, pp. 69-93.
[21] T.A.Chu,«Synthesis of hazard-free control circuits from asynchronous finite state machines specifications», Journal of VLSI Signal Processing, vol. 7, 1994, pp. 61-84.
[22] T.H.Meng,R.W. Brodersen, D.G.Messerschmitt, «Automatic synthesis of asynchronous circuits from high-level specifications», IEEE Transactions on Computer-Aided Design, vol. 8, n°11, November 1989, pp. 1185-1205.
[23] F. Robin, «Etuded'architecturesVLSInumériques parallèles etasynchrones pour la mise en oeuvre de nouveaux algorithmes d'analyse etrendu d'images», Thèse dedoctoratde l'ENST Paris, spécialitéElectronique et Communications, 27 octobre 1997.