A Novel Switched Capacitor Boost Derived Multilevel Hybrid Converter Modeling and Analysis

A Novel Switched Capacitor Boost Derived Multilevel Hybrid Converter Modeling and Analysis

Segaran Jeyasudha*Balakrishnan Geethalakshmi 

Department of Electrical and Electronics Engineering, Pondicherry Engineering College, Pondicherry Central University, Puducherry, India

Corresponding Author Email: 
jeyasudha_s@pec.edu
Page: 
199-206
|
DOI: 
https://doi.org/10.18280/ejee.210211
Received: 
12 January 2019
|
Accepted: 
9 March 2019
|
Published: 
30 June 2019
| Citation

OPEN ACCESS

Abstract: 

This paper investigates a novel high gain low power converter called switched capacitor boost derived multilevel hybrid converter (SCBDMHC) which produces dc and multilevel ac outputs simultaneously for solar PV application. The mathematical modelling of the SCBDMHC is derived using state space analysis and verified with the simulated results.  A closed loop control scheme of the circuit is implemented by the PI control logic. The robustness of the converter is tested with source variation, load variation and reference variation. The simulation results prove that the SCBDMHC produces the higher ac gain which is $\frac{2-\delta}{1-\delta}$ times more than the conventional MLI. So this SCBDMHC may implement for the high gain converter of the solar PV system.

Keywords: 

boost converter, boost derived hybrid converter, multilevel inverter, switched capacitor converter, PI controller

1. Introduction

The solar photovoltaic system is a promising and predominant system among all the renewable energy sources [1]. The low output voltage provided by the SPV system has to be boosted and inverted for dc and ac applications respectively [2]. The output of a single voltage source inverter is not adequate for medium and high power applications as it depends on the amplitude of the input source voltage. For such applications, VSI is cascaded as a multilevel inverter [3] and solar photovoltaic-based cascaded multilevel inverter is a serious research in the recent days. Compared to neural point clamped MLI and flying capacitor MLI, the cascaded configuration uses lesser number of devices for an increase in number of levels [4-5]. Nowadays researchers mainly focus on the design of reduced switch cascaded MLI [6] and hybrid MLI [7] topologies to extract the higher number of output voltage levels. Boost derived multilevel hybrid converter is one of the hybrid MLI proposed in [8] which produces multilevel ac output along with dc output. It is formed by cascading two or more BDHC [9]. A switched capacitor (SC) cell is connected in front of the BDHC is called as SCBDHC. For achieving higher ac gain in the multilevel configuration, SCBDHC units are connected serially and the configuration is referred as switched capacitor boost derived multilevel hybrid converter (SCBDMHC).

The SCBDMHC is a triple output and single input converter, which produces multilevel ac output and two boosted dc outputs simultaneously. This paper explains the proposed circuit configuration, its modes of operation, dynamic model and the closed loop control scheme. The robustness of the SCBDMHC is verified with load, line and reference variation.

This paper is structured into seven sections. Section 2 describes the circuit operation while Section 3 focuses on switching strategy. Section 4 explains the dynamic model of the converter and Section 5 presents closed loop PI controller design. The simulated results are explained in Section 6. Section 7 provides a fair summing of all the Sections.

2. Proposed Converter-SCBDMHC

2.1 Circuit configuration

Figure 1. Proposed SCBDMHC circuit

In the configuration of the proposed converter depicted in Figure 1, two SCBDHC units are connected in series to produce the five level ac output and separate dc outputs simultaneously. The switched capacitor cell has two switches S11 and S12, a capacitor Cs1, a diode Ds1 and a source resistor Rs1 for first level circuit. The input sources Vidc1 and Vidc2, bridge network switches Q11 to Q14, Q21 to Q24 and SC cell switches S11, S12, S21, and S22 are operated for both ac and dc operations. In the conventional multilevel inverter, the output phase voltage is the sum of the input voltages where as in the proposed SCBDMHC, as the input voltages are boosted by the switched capacitor cell which present in the input side, the output phase voltage is the boosted sum of the input voltages. Besides, each bridge along with the switched capacitor circuit produces separate boosted dc output along with the multilevel ac output.

2.2 Modes of operation

The circuit is operated with two modes: boosting mode and inverting mode.

2.2.1 Boosting mode

Boosting mode is a high frequency switching mode, which is further divided into shoot-through interval mode (0 < t < δT) and power interval mode (δT < t < (1-δ) T) where δ is the duty ratio. When the same leg of switches Q11, Q14 and the SC cell switch S12 are ON as shown in the Figure 2, the converter operates in shoot-through interval mode and when the switches Q11, Q12 and S11 are ON as shown in the Figure 3, the converter operates in power interval mode. During shoot-through interval, the capacitors Cs1 and Cs2 get charged and the inductors L1 and L2 store energy from the source. The diode D1 and D2 get reverse biased. Hence no current flows from source to dc load as well as ac load. During the power interval mode, the source current is divided and flowing through the dc and ac loads.

Figure 2. Shoot-through interval mode of SCBDMHC

2.2.2 Inverting mode

The inverting mode is a low frequency switching mode. This mode is further divided into level 1 and level 2 intervals. During level 1 interval, the switches Q11, Q12 and Q21 conduct and the first input source Vidc1 connects with the ac load, which provides three level output across Rac. During level 2 interval, the switches Q11, Q12, Q21 and Q22 conduct and the input sources Vidc1 and Vidc2 connect with the ac load, which provides five level output across Rac. Each phase level internally consists of boosting operation.

Figure 3. Power interval mode of SCBDMHC

2.3 Output voltages of SCBDMHC

In SCBDMHC, identical elements in each cell are assumed to have same values, for e.g. L1=L2Rdc1=Rdc2 etc. The number of voltage levels (m) in the phase voltage of SCBDMHC is m=(2N+1), where N is the number of SCBDHC units. The SCBDMHC dc output voltage of each cell is given in the equation (1):

$V_{o d c 1}(t)=\frac{(2-\delta) V_{i d c 1}(t)}{1-\delta} ; V_{o d c 2}(t)=\frac{(2-\delta) V_{i d c 2}(t)}{1-\delta}$   (1)

The five level SCBDMHC ac peak output voltage is given in the equation (2):

$v_{o a c}(t)=\frac{(2-\delta) V_{i d c 1}(t)}{1-\delta}+\frac{(2-\delta) V_{i d c 2}(t)}{1-\delta}$  (2)

In general, it is expressed as:

$v_{o a c}(t)=\sum_{m=1}^{N} \frac{(2-\delta) V_{i d c m}(t)}{1-\delta}=\sum_{m=1}^{N} V_{o d c m}(t)$   (3)

From the equations (1) to (3), it is understood that the dc and ac outputs of SCBDMHC is controlled by the duty cycle δ and the ac peak voltage depends on the dc output voltage.

3. Switching Strategy

The switching sequence adopted for the SCBDMHC is tabulated in the Table 1. The reference voltage is a sinusoidal waveform with the frequency f0 and the amplitude ma, called modulation index. For SCBDMHC the ma has the range of 0< ma<0.5. The output phase voltage has its fundamental component vf(t) at f0 and can be expressed as in (4):

$v_{f}(t)=\cdot m_{a} N V_{i d c} \cdot \sin \left(2 \pi f_{0} t\right) \cdots$ (4)

Table 1. Switching sequence of SCBDMHC

 

 

Switching sequences

AC Output Voltage Voac

Q11

Q12

Q13

Q14

Q21

Q22

Q23

Q24

0

B

0

0

B

B

0

0

B

0V

Positive Half

1

1

1

0

B

1

B

0

B

$\frac{(2-\delta) V_{i d c 1}}{1-\delta}$

2

1

1

0

B

1

1

0

B

$\frac{\left(V_{i d c 1}+V_{i d c 2}\right)(2-\delta)}{1-\delta}$

0

0

B

B

0

0

B

B

0

0V

Negative Half

1

0

B

1

1

0

B

1

0

$\frac{-(2-\delta) V_{i d c 1}}{1-\delta}$

2

0

B

1

1

0

B

1

1

$\frac{-\left(V_{i d c 1}+V_{i d c 2}\right)(2-\delta)}{1-\delta}$

 

This reference signal is compared with the two dc constants Va1, Va2 as shown in the Figure 4 to control the level of the SCBDMHC. A triangular carrier pulse Vtri is compared with a dc signal Vd, as shown in Figure 5, which controls the boosting period of SCBDMHC. The signals so generated separately for inverter operation and boost operation are logically added as shown in the Figure 6, and the appropriate gate pulses G11 to G14 and G21 to G24 are produced.

Figure 4. Generation of pulses for inverting operation of SCBDMHC

4. Dynamic Model of SCBDMHC

4.1 Mathematical modeling of the SCBDMHC

4.1.1 Level1 equations

The dynamic model of the SCBDMHC is derived to develop the transfer function of the system. Level 1 represents the first source that is connected with the ac load by operating the corresponding switches as given in the Table 1. The shoot-through interval mode and power interval mode dynamic equations are derived by applying the KVL and KCL, and are described in (5) to (8):

During shoot-through interval (0<t <δT)

$C_{s 1} \frac{d v_{c s 1}(t)}{d t}=\frac{V_{i d c 1}(t)}{R_{s 1}}-\frac{v_{c s 1}(t)}{R_{s 1}}-i_{L 1}(t)$

$C_{s 2} \frac{d v_{c s 2}(t)}{d t}=\frac{V_{i d c 2}(t)}{R_{s 2}}-\frac{v_{c s 2}(t)}{R_{s 2}}-i_{L 2}(t)$

$L_{1} \frac{d i L_{1}(t)}{d t}=v_{c s 1}(t), L_{2} \frac{d i L_{2}(t)}{d t}=v_{c s 2}(t)$

$C_{1} \frac{d v_{o d c 1}(t)}{d t}=-\frac{V_{o d c 1}(t)}{R_{d c 1}}, C_{2} \frac{d V_{o d c 2(t)}}{d t}=-\frac{V_{o d c 2(t)}}{R_{d c 2}}$   (5)

Figure 5. Generation of pulses for boosting operation of SCBDMHC

Figure 6. Logic diagram for gate pulses of SCBDMHC

During power interval (δT<t<(1-δ)T)

$C_{s 1} \frac{d v_{c s 1}(t)}{d t}=i_{L 1}(t), \quad C_{s 2} \frac{d v_{c s 2(t)}}{d t}=i_{L 2}(t)$

$L_{1} \frac{d i_{L 1}(t)}{d t}=V_{i d c 1}(t)+v_{c s 1}(t)-V_{o d c 1}(t)$

$L_{2} \frac{d i L_{2}(t)}{d t}=V_{i d c 2}(t)+v_{c s 2}(t)-V_{o d c 2}(t)$

$C_{1} \frac{d V_{o d c 1}(t)}{d t}=i_{L 1}(t)-i_{a c}(t)-\frac{V_{o d c 1}(t)}{R_{d c 1}}$

$C_{2} \frac{d V_{o d c 2}(t)}{d t}=i_{L 2}(t)-i_{a c}(t)-\frac{V_{o d c 2}(t)}{R_{d c 2}}$   (6)

where iL1, iL2 are the input current through the inductor L1 and L2 respectively. The inverter side equation is given in (7):

$L_{1} \frac{d i_{a c}(t)}{d t}=V_{i d c 1}(t)+v_{c s 1}(t)-R_{a c} i_{a c}(t)$    (7)

4.1.2 Level 2 equations

For the level 2, the boosting mode equations are similar as in the equations (5) and (6), the inverting side equation is given in (8):

$\left(L_{1}+L_{2}\right) \frac{d i_{a c}(t)}{d t}=V_{i d c 1}(t)+V_{i d c 2}(t)+v_{c s 1}(t)+v_{c s 2}(t)-R_{a c} i_{a c}(t)$    (8)

4.2 State-space representation

The system descriptive equations (5) to (8) are rearranged in the form of state equations. The level 1 averaged state equation is given in (9). Similarly the level 2 state and output equations are given in (10) and (11) respectively. In general, the level n state and output equations for SCBDMHC are given in the equations (12) and (13) respectively.

$\left(\begin{array}{c}{\frac{d v_{c s 1}}{d t}} \\ {\frac{d v_{c s 2}}{d t}} \\ {\frac{d i L_{1}}{d t}} \\ {\frac{d i L_{2}}{d t}} \\ {\frac{d V_{odc1}}{d t}} \\ {\frac{d V_{o d c 2}}{d t}} \\ {\frac{d i_{a c}}{d t}}\end{array}\right)=$$\left(\begin{array}{ccccccc}{\frac{-\delta}{R_{s 1} C_{s 1}}} & {0} & {\frac{1-2 \delta}{C_{s 1}}} & {0} & {0} & {0} & {0} \\ {0} & {\frac{-\delta}{R_{s 2} C_{s 2}}} & {0} & {\frac{1-2 \delta}{C_{s 2}}} & {0} & {0} & {0} \\ {\frac{1}{L_{1}}} & {0} & {0} & {0} & {\frac{-(1-\delta)}{L_{1}}} & {0} & {0} \\ {0} & {\frac{1}{L_{2}}} & {0} & {0} & {0} & {\frac{-(1-\delta)}{L_{2}}} & {0} \\ {0} & {0} & {\frac{(1-\delta)}{C_{1}}} & {0} & {\frac{-1}{C_{1} R_{d c 1}}} & {0} & {-\frac{(1-\delta)}{C_{1}}} \\ {0} & {0} & {0} & {\frac{(1-\delta)}{C_{2}}} & {0} & {\frac{-1}{C_{2} R_{d c 2}}} & {-\frac{(1-\delta)}{C_{1}}} \\ {\frac{(1-\delta)}{L_{1}}} & {0} & {0} & {0} & {0} & {0} & {\frac{-(1-\delta) R_{a c}}{L_{1}}}\end{array}\right)$ $\left(\begin{array}{c}{v_{\operatorname{cs} 1}} \\ {v_{\operatorname{cs} 2}} \\ {i_{L 1}} \\ {i_{L 2}} \\ {V_{o d c 1}} \\ {V_{o d c 2}} \\ {i_{a c}}\end{array}\right)$$+\left(\begin{array}{cc}{\frac{\delta}{R_{s 1} c_{s 1}}} & {0} \\ {0} & {\frac{\delta}{R_{s 2} c_{s 2}}} \\ {\frac{(1-\delta)}{L_{1}}} & {0} \\ {0} & {\frac{(1-\delta)}{L_{2}}} \\ {0} & {0} \\ {0} & {0} \\ {\frac{(1-\delta)}{L_{1}}} & {0}\end{array}\right)\left(\begin{array}{c}{V_{i d c 1}} \\ {V_{i d c 2}}\end{array}\right)$ (9)

$\left(\begin{array}{c}{\frac{d v_{c s 1}}{d t}} \\ {\frac{d v_{c s 2}}{d t}} \\ {\frac{d i L_{1}}{d t}} \\ {\frac{d i L_{2}}{d t}} \\ {\frac{d V_{odc1}}{d t}} \\ {\frac{d V_{o d c 2}}{d t}} \\ {\frac{d i_{a c}}{d t}}\end{array}\right)=$$\left(\begin{array}{ccccccc}{\frac{-\delta}{R_{s 1} C_{s 1}}} & {0} & {\frac{1-2 \delta}{C_{s 1}}} & {0} & {0} & {0} & {0} \\ {0} & {\frac{-\delta}{R_{s 2} C_{s 2}}} & {0} & {\frac{1-2 \delta}{C_{s 2}}} & {0} & {0} & {0} \\ {\frac{1}{L_{1}}} & {0} & {0} & {0} & {\frac{-(1-\delta)}{L_{1}}} & {0} & {0} \\ {0} & {\frac{1}{L_{2}}} & {0} & {0} & {0} & {\frac{-(1-\delta)}{L_{2}}} & {0} \\ {0} & {0} & {\frac{(1-\delta)}{C_{1}}} & {0} & {\frac{-1}{C_{1} R_{d c 1}}} & {0} & {-\frac{(1-\delta)}{C_{1}}} \\ {0} & {0} & {0} & {\frac{(1-\delta)}{C_{2}}} & {0} & {\frac{-1}{C_{2} R_{d c 2}}} & {-\frac{(1-\delta)}{C_{1}}} \\ {\frac{(1-\delta)}{L_{1}+L_2}} & {0} & {0} & {0} & {0} & {0} & {\frac{-(1-\delta) R_{a c}}{L_{1}+L_2}}\end{array}\right)$ $\left(\begin{array}{c}{v_{\operatorname{cs} 1}} \\ {v_{\operatorname{cs} 2}} \\ {i_{L 1}} \\ {i_{L 2}} \\ {V_{o d c 1}} \\ {V_{o d c 2}} \\ {i_{a c}}\end{array}\right)$$+\left(\begin{array}{cc}{\frac{\delta}{R_{s 1} c_{s 1}}} & {0} \\ {0} & {\frac{\delta}{R_{s 2} c_{s 2}}} \\ {\frac{(1-\delta)}{L_{1}}} & {0} \\ {0} & {\frac{(1-\delta)}{L_{2}}} \\ {0} & {0} \\ {0} & {0} \\ {\frac{(1-\delta)}{L_{1}+L_2}} & {\frac{(1-\delta)}{L_{1}+L_2}}\end{array}\right)\left(\begin{array}{c}{V_{i d c 1}} \\ {V_{i d c 2}}\end{array}\right)$ (10)

$y(t)=\left(\begin{array}{lllllll}{1} & {1} & {0} & {0} & {1} & {1} & {0}\end{array}\right)\left(\begin{array}{c}{v_{c s 1}} \\ {v_{c s 2}} \\ {i_{L 1}} \\ {i_{L 2}} \\ {V_{o d c 1}} \\ {V_{o d c 2}} \\ {i_{a c}}\end{array}\right)$  (11)

$\left(\begin{array}{c}{\frac{d v_{c s 1}}{d t}} \\ {\frac{d v_{c s 2}}{d t}} \\ {\vdots}\\{\frac{d v_{c s n}}{d t}} \\{\frac{d i L_{1}}{d t}} \\ {\frac{d i L_{2}}{d t}} \\ {\vdots}\\{\frac{d i L_{n}}{d t}} \\{\frac{d V_{odc1}}{d t}} \\ {\frac{d V_{o d c 2}}{d t}} \\ {\vdots}\\{\frac{d V_{odcn}}{d t}} \\{\frac{d i_{a c}}{d t}}\end{array}\right)=$$\left(\begin{array}{ccccccccc}{\frac{-\delta}{R_{s 1} C_{s 1}}} & {0} & {\frac{1-2 \delta}{C_{s 1}}} & {0} & {0} & {0} & {0} & {\cdots} & {0}\\ {0} & {\frac{-\delta}{R_{s 2} C_{s 2}}} & {0} & {\frac{1-2 \delta}{C_{s 2}}} & {0} & {0} & {0} & {\cdots} & {0}\\ {0}& {0} &{\ddots} & {\vdots } &  {\ddots } &  {\vdots } & {0} & {\cdots} & {\vdots }\\ {0}& {0} &{\cdots} & {\frac{-\delta}{R_{s 2} C_{s n}}} & {\cdots} & {\frac{1-2 \delta}{C_{s n}}} & {0}& {\cdots} & {0}\\ {\frac{1}{L_{1}}} & {0} & {0} & {0} & {\frac{-(1-\delta)}{L_{1}}} & {0} & {0} & {\cdots} & {0}\\ {0} & {\frac{1}{L_{2}}} & {0} & {0} & {0} & {\frac{-(1-\delta)}{L_{1}}} & {0} & {\cdots} & {0}\\ {0}& {0} &{\ddots} & {\vdots } &  {0 } &  {0 } & {\ddots } & {\vdots} & {\vdots }\\ {0}& {0} &{\cdots} & {\frac{1}{L_{n}}} & {0}& {0} &{\cdots} &{\frac{-(1-\delta)}{L_{n}}} &{0}\\ {0} & {0} & {\frac{(1-\delta)}{C_{1}}} & {0} & {\frac{-1}{C_{1} R_{d c 1}}} & {0} &{0} &{0} & {-\frac{(1-\delta)}{C_{1}}}\\ {0} & {0} & {0} & {\frac{(1-\delta)}{C_{2}}} & {0} & {\frac{-1}{C_{2} R_{d c 2}}} & {0} &{0} & {-\frac{(1-\delta)}{C_{2}}}\\ {0}& {0} &{0} & {0} &  {\ddots } &  {\vdots } & {\ddots } & {\vdots} & {\vdots }\\{0}& {0} &{0} & {0} &  {\cdots }&{\frac{(1-\delta)}{C_{n}}} &{\cdots }&{\frac{-1}{C_{n} R_{d c n}}} &{\frac{(1-\delta)}{C_{n}}}\\ {\frac{(1-\delta)}{L_{1}+L_2+\cdots+L_n}} & {0} & {0} & {0} & {0} & {0} & {0} & {\cdots} &{\frac{-(1-\delta) R_{a c}}{L_{1}+L_2+\cdots+L_n}}\end{array}\right)$$\left(\begin{array}{c}{v_{\operatorname{cs} 1}} \\ {v_{\operatorname{cs} 2}} \\ {\vdots}\\ {v_{\operatorname{cs} n}} \\{ i_{L 1}} \\ {i_{L 2}} \\{\vdots}\\{i_{L n}} \\ {V_{o d c 1}} \\ {V_{o d c 2}} \\{\vdots}\\ {V_{o d c n}} \\{i_{a c}}\end{array}\right)$$+\left(\begin{array}{cccc}{\frac{\delta}{R_{s 1} c_{s 1}}} & {0} & {\cdots} & {0}\\ {0} & {\frac{\delta}{R_{s 2} c_{s 2}}} & {\cdots} & {0}\\ {0} & {0} &{\ddots} & {\vdots}\\ {0} & {0} &{\cdots} & {\frac{\delta}{R_{s 2} c_{s 2}}}\\ {\frac{(1-\delta)}{L_{1}}} & {0} & {\cdots} & {0}\\ {0} & {\frac{(1-\delta)}{L_{1}}} & {\cdots} & {0}\\ {0} & {0} &{\ddots} & {\vdots}\\ {0} & {0} &{\cdots} & {\frac{(1-\delta)}{L_{1}}}\\ {0} & {0} & {\cdots} & {0}\\ {0} & {0} & {\cdots} & {0}\\ {0} & {0} &{\ddots} & {\vdots}\\ {0} & {0} & {\cdots} & {0}\\ {\frac{(1-\delta)}{L_{1}+L_2+{\cdots}+L_n}} & {\frac{(1-\delta)}{L_{1}+L_2+{\cdots}+L_n}} & {\cdots} &{\frac{(1-\delta)}{L_{1}+L_2+{\cdots}+L_n}} \end{array}\right)\left(\begin{array}{c}{V_{i d c 1}} \\ {V_{i d c 2}}\\ {\vdots}\\{V_{i d c n}}\end{array}\right)$(12)

$(t)=\left(\begin{array}{llllllll}{1 \cdots} & {1} & {0} & {\cdots} & {0} & {1} & {\cdots} & {1} & {0}\end{array}\right)$$\left(\begin{array}{c}{v_{c s 1}}\\{v_{c s 2}}\\{\vdots}\\{v_{c s n}}\\{i_{L 1}}\\{i_{L 2}}\\{\vdots}\\{i_{L n}}\\{V_{o d c 1}}\\{V_{o d c 2}}\\{\vdots}\\{V_{o d c n}}\\{i_{a c}}\end{array}\right)$(13)

Linearizing (5) to (8) by adding the small perturbation in the input, output and state variables, around the equilibrium point and separating the dynamic ac small signal terms from the dc steady state component as in [10], the following dynamic model (14) is obtained:

$\dot{x}(t)=A \hat{x}(t)+B \hat{u}(t)+E \hat{\delta}(t)$   (14)

where the state matrix A and the input matrix B are given in (10). E matrix corresponding to $\hat{\delta}(t)$, $\hat{x}(t)$ and $\hat{u}(t)$ are given in (15):

$E=$$\left(\begin{array}{c}{\frac{V_{i d c 1}-V_{c s 1}}{R_{s 1} C_{s 1}}-\frac{2 I_{L 1}}{C_{s 1}}} \\ {\frac{V_{i d c 2}-V_{c s 2}}{R_{s 2} C_{s 2}}-\frac{2 I_{L 2}}{C_{s 2}}} \\ {-\frac{V_{i d c 1}}{L 1}+\frac{V_{o d c 1}}{L 1}}\\{-\frac{V_{i d c 2}}{L 2}+\frac{V_{o d c 2}}{L 2}}\\{\frac{-I_{L 1}+I_{a c}}{C_{1}}}\\{\frac{-I_{L 2}+I_{a c}}{C_{2}}}\\{\frac{-V_{i d c 1}-V_{i d c 2}-V_{c s 1}-V_{c s 2}+R_{a c} I_{a c}}{L_{1}+L_{2}}}\end{array}\right) \hat{x}(t)$$= \left(\begin{array}{c}{\hat{v}_{c s 1}} \\ {\hat{v}_{c s 2}} \\ {\hat{\imath}_{L 1}} \\ {\hat{\imath}_{L 2}} \\ {\hat{\imath}_{o d c 1}} \\ {\hat{v}_{o d c 2}} \\ {\hat{\imath}_{a c}}\end{array}\right) \widehat{u}(t)=\left(\begin{array}{l}{\hat{v}_{i d c 1}} \\ {\hat{v}_{i d c 2}}\end{array}\right)$    (15)

4.3 Numerical validation

The parameters considered for the simulation of SCBDMHC are specified in Table 2. These values are substituted in the equation (10) and the resultant state and input matrices obtained are given in equation (16).

Table 2. Parameters of SCBDMHC

Paraameters

Values

Input Voltage (Vidc1 and Vidc2)

40V

Input Inductor (L1 and L2)

5mH

DC Capacitor (C1 and C2)

1mF

DC load resistor (Rdc1 and Rdc2)

20Ω

AC load resistor (Rac)

50Ω

Switching frequency (f)

10KHz

Switched capacitor (Cs1 and Cs2)

1mF

Source Resistor (Rs1 and Rs2)

0.01 Ω

 

$A=\left(\begin{array}{ccccccc}{-51000} & {0} & {-20} & {0} & {0} & {0} & {0} \\ {0} & {-51000} & {0} & {-20} & {0} & {0} & {0} \\ {200} & {0} & {0} & {0} & {-98} & {0} & {0} \\ {0} & {200} & {0} & {0} & {0} & {-98} & {0} \\ {0} & {0} & {490} & {0} & {-50} & {0} & {-490} \\ {0} & {0} & {0} & {490} & {0} & {-50} & {-490} \\ {49} & {0} & {0} & {0} & {0} & {0} & {-2450}\end{array}\right)$

$B=\left(\begin{array}{cc}{51000} & {0} \\ {0} & {51000} \\ {98} & {0} \\ {0} & {98} \\ {0} & {0} \\ {0} & {0} \\ {98} & {98}\end{array}\right) U=\left(\begin{array}{c}{40} \\ {40}\end{array}\right)$

$C=\left(\begin{array}{lllllll}{1} & {1} & {0} & {0} & {1} & {1} & {0}\end{array}\right), D=(0)$(16)

To solve the state equations, m-file programming in MATLAB is used and the state values obtained is given in equation (17):

$x(t)=\left(v_{c s 1}(t) \quad v_{c s 2}(t) \quad i_{L 1}(t) \quad i_{L 2}(t) V_{o d c_{1}}(t) \quad V_{o d c_{2}}(t) \quad i_{a c}(t)\right)^{T}$  

$x(t)=(39.9936 V \quad 39.9936 V \quad 16.41 A \quad 16.41 A \quad 121.6195 V \quad 121.6195 V \quad 3.9 A)^{T}$    (17)

In order to validate the developed model of the system, the circuit is simulated using MATLAB/Simulink with the same parameters specified in Table 2. Input voltage is set to 40V with the duty ratio of 0.51 and modulation index of 0.49. The simulated output voltage across the loads and current through the loads observed are depicted in the Figure 7 and Figure 8 respectively.  These results are tabulated in the Table 3 and compared with the values obtained from the mathematical model.

Figure 7. Open loop input and output voltage waveforms

Figure 8. Open loop input and output current waveforms

Table 3. Model validation of SCBDMHC

Parameters

Values

Theoretical

Simulated

Output dc voltage (Vodc1 and Vodc2)

121V

121.62 V

Output ac voltage (Voac)

195V

179V

Input Current (iL1 to iL2)

16.4A

17.4 A

Output dc current

(idc1 to idc2)

6.08 A

6.0 A

Output ac current (iac)

3.9A

3.54A

 

From the Figure 7 the output dc voltage is found to be 121.62 V and the ac voltage is 179 V. Similarly from Figure 8 the input current is noted as 17.4 A, the dc output current is 6 A and ac the output current is 3.54 A.

The proposed SCBDMHC output voltage is compared with the conventional MLI. When 40 V dc is supplied as input for the five level multilevel inverter, it produces the ac peak output of 80 V, whereas the five level SCBDMHC, produced the ac output peak voltage of 243 V. This will be $\frac{2-\delta}{1-\delta}$ times higher than the conventional MLI output.

4.4 Transfer function

Using the equations (14) and the Table 2 the dc output voltage to control transfer function (18) is developed.

$\frac{V_{\text {odc}}(s)}{\delta(s)}=\frac{-1.25 \times 10^{4} s^{6}-1.3 \times 10^{9} s^{5}-3.8 \times 10^{13} s^{4}-1.48 \times 10^{17} s^{3}+4.15 \times 10^{19} s^{2}-4.5 \times 10^{21} s+2.43 \times 10^{24}}{s^{7}+104550 s^{6}+2.861 \times 10^{9} s^{5}+6.668 \times 10^{12} s^{4}+9.197 \times 10^{14} s^{3}+6.42 \times 10^{17} s^{2}+3.727 \times 10^{19} s+1.47 \times 10^{22}}$   (18)

5. Closed Loop Scheme of SCBDMHC

Figure 9 shows the closed loop control scheme of the switched capacitor boost derived multilevel hybrid converter. A part of dc output voltage is fed back from the SCBDMHC and compared with the set point value, and the error occurred is processed by the PI controller [11] whose parameters are tuned using Zeigler Nichols oscillation method. The controller parameters Kp=0.0072 and Ki=5.01 are obtained. The simulation results with the closed loop circuit is discussed in the next section. 

Figure 9. Closed loop scheme of SCBDMHC

6. Simulation Results and Analysis

The closed loop system of the SCBDMHC is tested with line regulation, load regulation and reference variation.

6.1 Line regulation of SCBDMHC

To verify the performance of the controller under supply variations, the load resistance is kept at a fixed value of Rdc=20 Ω and Rac=50 Ω, variation is incorporated only in the supply side. The reference voltage across the dc load is set as 150 V. The supply voltage is maintained at 45V until t=0.75s and a step change is given to vary the input voltage to 35 V. The corresponding dc output voltage is regulated to 150 V as depicted in Figure 10. The ac output voltage is also regulated for 230 V as shown in the Figure 6c

Figure 10. Supply variation - SCBDMHC

6.2 Load regulation of SCBDMHC

The input voltage is set as 40 V and the reference dc output voltage is at 150 V and ac output voltage is at 230 V. Under this condition, the dc load is varied from 5 Ω to 25 Ω at 0.75 sec as shown in the Figure 11(a).

Figure 11. DC load variation – SCBDMHC

The sudden rise in the load resistance, results in a corresponding peak overshoot to 250V in the output voltage, which gives a significant variation from the desired set value of 150 V. The controller responds instantaneously and adjusts the duty ratio in order to generate an output voltage to the desired set reference value, within a settling time of ts=0.25 sec as depicted in Figure 11(b). To support this result, the corresponding variation in the load current has also been presented in Figure 11(c) and it decreases from 30 A to 6 A. Similarly, ac load resistance Rac is varied from 40 Ω to 80 Ω at the time t=0.75 sec. For a sudden increase in load, the controller responds effectively and it is observed that the output voltage is maintained constant, irrespective of the change in load providing load regulation as shown in Figure 12(b). The corresponding variation in the load current is presented in Figure 12(c) and it is reduced from 5.75 A to 2.8 A.

Figure 12. AC load variation - SCBDMHC

6.3 Reference variation of SCBDMHC

Here both the input supply voltage and load resistance are maintained constant and the controller performance is verified by varying the reference value. DC input voltage is fixed at 40 V and load resistance values are maintained at Rdc=20 Ω and Rac=50 Ω. For dc side, initially, the reference voltage is set at 200V and the reference value is changed to 150 V at t=0.75 sec. Similarly the ac output voltage reference varies from 282.9 V to 212.1 V rms at t=0.75 sec. The dc and ac output voltage waveforms depicted in Figure 13, reveal the controller performance in tracking the respective set reference values.

Figure 13. Reference variation - SCBDMHC

7. Conclusion

In this paper, a novel switched capacitor boost derived multilevel hybrid converter is proposed which is capable of supplying boosted dc and multilevel ac output simultaneously for SPV application. The state-space modeling equations are derived and validated with the simulated results. A closed loop scheme for the SCBDMHC has been developed and to prove its robustness the system performance is tested with line regulation, load regulation and reference variation. From the results, it is concluded that the SCBDMHC has the higher ac gain which is $\frac{2-\delta}{1-\delta}$ times more than the conventional MLI.

Nomenclature

Vidc1, Vidc2

Input sources

v(t)

A dc signal

V1, V2

dc reference signals for level triggering V

L1, L2

 Inductors H

m

Number of input phase voltage

ma

Modulation index

x

State vector matrix

Vodc

Output voltage of the DC load V

Voac

Output voltage of the AC load V

Q11 to Q14

Bridge network switches for I stage

Q21 to Q24

Bridge network switches for II stage

Rac

AC load resistor

Rdc

DC load resistor

s

Laplace Transform factor

T

Simulation time period

Vodc1, Vodc3

Voltage across capacitors C1 to C3

$\hat{v}\,\,(t)$

Small signal AC variations for V(t)

Greek symbol

δ

Duty ratio

Subscripts

odc

Output dc

oac

Output ac

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