A Low Noise and Power Efficient 45nm GPDK Technology based Highly Stable Current Balancing Logic (HCBL) and Dynamic Logic Circuits for Mixed Signal Systems

A Low Noise and Power Efficient 45nm GPDK Technology based Highly Stable Current Balancing Logic (HCBL) and Dynamic Logic Circuits for Mixed Signal Systems

S. Seenuvasamurthi G. Nagarajan

Department of ECE, Research Scholar, Pondicherry University, India, Pondicherry Engineering College, Pondicherry

Department of ECE, Professor, Pondicherry University, India, Pondicherry Engineering College, Pondicherry

Corresponding Author Email: 
seenu_er@yahoo.co.in; nagarajanpec@pec.edu
Page: 
213-226
|
DOI: 
https://doi.org/10.18280/ama_c.720402
Received: 
12 December 2016
|
Accepted: 
15 February 2017
|
Published: 
31 December 2017
| Citation

OPEN ACCESS

Abstract: 

Noise is an important factor in the analog and digital circuits which determine the characteristics of the system. There are many sources of noises. Power supply noise caused by circuit switching, crosstalk noise due to capacitive coupling between neighboring interconnects, fluctuations in device parameters due to process variations, noise due to charge sharing and charge leakage in high speed dynamic logic circuits. The work aims at developing a noise robust circuit with high frequency response. The same circuit can be implemented in a dynamic logic system with reduced number of transistor. Also, the dynamic logic will have the probability of signal switching activity to be low which will subsequently reduce the power of the system. The circuits have been constructed using cadence ADE and the same has been simulated with Spectra using 45nm GPDK technology. The simulation results show that the power consumption has been reduced multi-fold and the bandwidth has been increased by 102 Hz and the delay is reduced by 50%

Keywords: 

Current Balanced Logic, pseudo-NMOS, Noise immunity, Dynamic logic

1. Introduction
2. Previous works
3. Proposed work
4. Simulation Results
Conclusion
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